AX88180 datasheet(46/47 Pages) ASIX

46 / 47 page

AX88180

ASIX ELECTRONICS CORPORATION

Revision History

Revision

Date

Comment

V1.0

2005/10/4

First edition

V1.0A

2006/3/31

1. Correct some typos in Section 3.4.

2. Correct the name definition of some pins in Section 1-3 and Section 2.

V1.1

2006/7/28

1. Some typo errors corrected between Pin diagram and tables.

2. Host read/write timing revised in Section 5.

3. Some bits of registers are updated.

4. Add some connections between MCU and AX88180 in Appendix.

5. Add wake up LAN in Appendix.

6. Update the power consumption information in Section 5.1.6.

V1.2

2007/3/28

1. Correct some information in Section 3.9 for 16-bit mode operation.

2. Modify the data access timing information in Section 5.2.5, 5.2.6 and

Appendix A4.

3. Update the power consumption information in Section 5.1.6.

4. Add some information in Section 3.10.

5. Define the bit filed name (RXJUBOLEN) for bit 10:7 of MAC_CFG1

6. Add AX88180 with Gigabit PHY Connection information in Appendix A3.

7. Modify some descriptions in Section 1.1, 4.6, 4.16, 4.17, 4.18, 4.22,

4.34~4.36, 4.40.

8. Modify the description of TXCLK and GTXCLK pin in Section 2.2.

9. Rearrange the content of Appendix into Appendix A1~A5.

10. Change the number format from 16h’XXXX to 0xXXXX for example.

V1.3

2007/5/4

Swap the pin definition of pin #90 and #91 in Section 2.6 and Figure 2.

Correct some typo errors of pin type in Table 1 and Table 5.

V1.4

2007/5/18

Modify max operation frequency of HCLK from 125MHz to 100MHz.

Modify some thermal information in Section 5.1.7.

AX88180 Datasheet(PDF) 46 Page - ASIX Electronics Corporation

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