AX88180 datasheet(26/47 Pages) ASIX

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AX88180

ASIX ELECTRONICS CORPORATION

4.28 MDIOCTRL--MDIO Control Register

Offset Address = 0xFC84

Default = 0x0000_0000

Field

Name

Type

Default

Description

31:16

All 0’s

Reserved

WTEN

R/W

Write Enable.

Driver enables this bit to issue a write cycle to PHY, it will be auto-cleared when

AX88180 finishes the write cycle

1 = enable

0 = disable

RDEN

R/W

Read Enable.

Driver enables this bit to issue a read cycle to PHY. This bit will be auto-cleared

when AX88180 finishes the read cycle

1 = enable

0 = disable

12:8

PHYCRIDX R/W

00000

PHY Register Index

Driver sets this field to define the internal register index of PHY when it accesses

PHY.

7:5

000

Reserved

4:0

PHYID

R/W

00000

PHY ID

Driver sets the PHY ID value in this field. AX88180 will refer to this field when

it accesses PHY by MDIO/MDC signals.

4.29 MDIODP--MDIO Data Port Register

Offset Address = 0xFC88

Default = 0x0000_0000

Field

Name

Type

Default

Description

31:16

All 0’s

Reserved

15:0

MDPORT R/W

All 0’s

PHY Data Port

To or from PHY data is put in this field.

4.30 GPIO_CTRL--GPIO Control Register

Offset Address = 0xFC8C

Default = 0x0000_0003

Field

Name

Type

Default

Description

31:10

All 0’s

Reserved

GPIO1S

R/W

GPIO1 Status

This bit stands for the pin status of GPIO1 when it is set to input mode.

1 = high state

0 = low state

GPIO0S

R/W

GPIO0 Status

This bit stands for the pin status of GPIO0 when it is set to input mode.

1 = high state

0 = low state

7:2

All 0’s

Reserved

GPIO1DIR R/W

GPIO1 Mode Direction

This field defines the direction of GPIO1 pin.

1 = input mode

0 = output mode

GPIO0DIR R/W

GPIO0 Mode Direction

This field defines the direction of GPIO pin.

1 = input mode

0 = output mode

Note: For output mode, software must firstly set the bit0 or bit1 to output mode then set bit8 or bit9.

AX88180 Datasheet(PDF) 26 Page - ASIX Electronics Corporation

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