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AX88180 Datasheet(PDF) 16 Page - ASIX Electronics Corporation |
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AX88180 Datasheet(HTML) 16 Page - ASIX Electronics Corporation |
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16 / 47 page ![]() AX88180 16 ASIX ELECTRONICS CORPORATION 4.1 CMD--Command Register Offset Address = 0xFC00 Default = 0x0000_0201 Field Name Type Default Description 31:16 - R/W All 0’s Reserved 15 RXVLAN R/W 0 RX VLAN indicator Driver enables this bit to indicate AX88180 that the received packet will include 4 bytes VLAN tag; AX88180 will skip 4 bytes when it calculates the checksum of IP, TCP or UDP packet. 1 = enable 0 = disable 14 TXVLAN R/W 0 TX VLAN indicator Driver enables this bit to indicate AX88180 that the transmitted packet will include 4 bytes VLAN tag; AX88180 will skip 4 bytes when it calculates the checksum of IP, TCP or UDP packet. 1 = enable 0 = disable 13:10 - R/W All 0’s Reserved 9 RXEN R/W 1 RX Function Enable When this bit is enabled, MAC starts to receive packets. 1 = enable 0 = disable 8 TXEN R/W 0 TX Function Enable When this bit is enabled, MAC could start to transmit packet to Ethernet. 1 = enable 0 = disable 7 - R/W 0 Reserved 6 INTMOD R/W 0 Interrupt Active Mode Driver sets this bit to indicate AX88180 the interrupt of system is activated high or low. 1: Active high 0: Active low 5:1 - R/W All 0’s Reserved 0 WAKEMOD R/W 1 WAKEUP pin polarity Driver sets this bit to indicate AX88180 the polarity of system wake-up signal is activated high or low. 1: Active high 0: Active low 4.2 IMR--Interrupt Mask Register Offset Address = 0xFC04 Default = 0x0000_0000 Field Name Type Default Description 31:6 - R All 0’s Reserved 5 PHYMASK R/W 0 PHY interrupt Mask When this bit is enabled, an interrupt request from PHY set in bit 5 of Interrupt Status Register will make AX88180 to issue an interrupt to host. 1 = enable 0 = disable 4 PRIM R/W 0 Packet Received Interrupt Mask When this bit is enabled, a received interrupt request set in bit 4 of Interrupt Status Register will make AX88180 to issue an interrupt to host. 1 = enable 0 = disable 3 PTIM R/W 0 Packet Transmitted Interrupt Mask When this bit is enabled, a transmitted interrupt request set in bit 3 of Interrupt Status Register will make AX88180 issue an interrupt to host. |
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