| Electronic Components Datasheet Search |
|
AX88180 Datasheet(PDF) 17 Page - ASIX Electronics Corporation |
|
|
|||||||||||||||||||||||||||||
AX88180 Datasheet(HTML) 17 Page - ASIX Electronics Corporation |
|
17 / 47 page ![]() AX88180 17 ASIX ELECTRONICS CORPORATION 1 = enable 0 = disable 2 - R/W 0 Reserved 1 DOGIM R/W 0 Watch Dog Timer Interrupt Mask When this bit is enabled, a watch dog timer expired interrupt request set in bit1 of Interrupt Status Register will make AX88180 to issue an interrupt to host 1 = enable 0 = disable 0 RXFULIM R/W 0 RX Buffer Full Interrupt Mask When this bit is enabled, a RX buffer full interrupt request set in bit 0 of Interrupt Status Register will make AX88180 to issue an interrupt to host. 1 = enable 0 = disable 4.3 ISR--Interrupt Status Register Offset Address = 0xFC08 Default = 0x0000_0000 Field Name Type Default Description 31:6 - R All 0’s Reserved 5 PHYIG R/W 0 PHY Interrupt Generation If this bit is set to ‘1’, it means there is an interrupt request from PHY. AX88180 will forward this interrupt to system. Meantime driver should poll PHY and adopt proper procedure. Write ‘1’ to this bit to clear this request status. 1 = have interrupt request 0 = no interrupt request 4 RPIG R/W 0 Receive Packet Interrupt Generation If this bit is set to ‘1’, it means AX88180 receives a packet or (packets) from PHY. The packet is kept in RX buffer. Write ‘1’ to this bit to clear this request status. 1 = have received packet 0 = no received packet 3 FTPI R/W 0 Finish Transmitting Packet Interrupt If this bit is set to ‘1’, it means AX88180 had transmitted packet to PHY. Write ‘1’ to this bit to clear this request status. 1 = finish transmission 0 = none 2 - R/W 0 Reserved 1 WDTEI R/W 0 Watch Dog Timer Expired Interrupt If this bit is set to ‘1’, it means the WATCH DOG timer is expired. AX88180 will issue an interrupt to host. Write ‘1’ to this bit to clear this request status. The expired duration can refer to DOGTHD0 and DOGTHD1 registers. 1 = timer expired happens 0 = none 0 RXFULI R/W 0 RX Buffer Full Interrupt If this bit is set to ‘1’ it means RX buffer is full and no more packets will be received until packets are read out. Write ‘1’ to this bit to clear this request status. 1 = RX buffer full 0 = None |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |