S9S08QD2CSC datasheet(104/198 Pages) FREESCALE

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Analog-to-Digital Converter (S08ADC10V1)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

104

Freescale Semiconductor

ADLPC

ADIV

ADLSMP

MODE

ADICLK

Reset:

Figure 8-10. Configuration Register (ADCCFG)

Table 8-5. ADCCFG Register Field Descriptions

Field

Description

ADLPC

Low Power Configuration — ADLPC controls the speed and power configuration of the successive

approximation converter. This is used to optimize power consumption when higher sample rates are not required.

0 High speed configuration

1 Low power configuration: {FC31}The power is reduced at the expense of maximum clock speed.

6:5

ADIV

Clock Divide Select — ADIV select the divide ratio used by the ADC to generate the internal clock ADCK.

Table 8-6 shows the available clock configurations.

ADLSMP

Long Sample Time Configuration — ADLSMP selects between long and short sample time. This adjusts the

sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for

lower impedance inputs. Longer sample times can also be used to lower overall power consumption when

continuous conversions are enabled if high conversion rates are not required.

0 Short sample time

1 Long sample time

3:2

MODE

Conversion Mode Selection — MODE bits are used to select between 10- or 8-bit operation. See Table 8-7.

1:0

ADICLK

Input Clock Select — ADICLK bits select the input clock source to generate the internal clock ADCK. See

Table 8-8.

Table 8-6. Clock Divide Select

ADIV

Divide Ratio

Clock Rate

Input clock

÷ 2

Input clock

÷ 4

Input clock

÷ 8

Table 8-7. Conversion Modes

MODE

Mode Description

8-bit conversion (N=8)

Reserved

10-bit conversion (N=10)

Reserved

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