DM9621 datasheet(34/66 Pages) DAVICOM

34 / 66 page

DM9621

USB2.0 to Fast Ethernet Controller

Preliminary

Version: DM9621 -14-DS-P02

February 23, 2011

symbol decoding functions) bypassed. Transmit functions

( symbol encoder and scrambler) bypassed

0 = Normal operation

BP_ADPOK

0, RW

BYPASS ADPOK :

Force signal detector (SD) active. This register is for debug only,

not release to customer.

1=Force SD is OK,

0=Normal operation

RESERVED

0, RO

Reserved:

Write as 0, ignore on read.

1, RW

100BASE-TX or FX mode control:

1 = 100BASE-TX operation

0 = 100BASE-FX operation

RESERVED

0, RO

Reserved

RESERVED

0, RO

Reserved:

Write as 0, ignore on read.

F_LINK_100

0, RW

Force good link in 100Mbps:

0 = Normal 100Mbps operation

1 = Force 100Mbps good link status

This bit is useful for diagnostic purposes.

RESERVED

0, RO

Reserved:

Write as 0, ignore on read.

RESERVED

0, RO

Reserved:

Write as 0, ignore on read.

RPDCTR-EN

1, RW

Reduced power down control enable:

This bit is used to enable automatic reduced power down.

0 : Disable automatic reduced power down.

1 : Enable automatic reduced power down.

SMRST

0, RW

Reset state machine:

When writes 1 to this bit, all state machines of PHY will be reset.

This bit is self-clear after reset is completed.

MFPSC

1, RW

MF preamble suppression control:

MII frame preamble suppression control bit

1 = MF preamble suppression bit on

0 = MF preamble suppression bit off

SLEEP

0, RW

Sleep mode:

Writing a 1 to this bit will cause PHY entering the Sleep mode and

power down all circuit except oscillator and clock generator circuit.

When waking up from Sleep mode (write this bit to 0), the

configuration will go back to the state before sleep; but the state

machine will be reset

Reserved

0, RW

Reserved

Force to 0 in application.

DM9621 Datasheet(PDF) 34 Page - Davicom Semiconductor, Inc.

DM9621 Datasheet(HTML) 34 Page - Davicom Semiconductor, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datasheet Download

Link URL