DM9621 datasheet(18/66 Pages) DAVICOM

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DM9621

USB2.0 to Fast Ethernet Controller

Preliminary

Version: DM9621 -14-DS-P02

February 23, 2011

4.7 Back Pressure Threshold Register (08H)

Bit

Name

Default

Description

7:4

BPHW

PHS3h, RW

Back Pressure High Water Overflow Threshold. MAC will generate the jam

pattern when RX SRAM free space is lower than this threshold value.

Default is 3K-byte free space. Please don’t exceed SRAM size.

(1 unit=1K bytes)

3:0

JPT

PHS7h, RW

Jam Pattern Time. Default is 100us.

bit3 bit2 bit1 bit0

time

0 0 0 0

2.5us

0 0 0 1

5us

0 0 1 0

7.5us

0 0 1 1

12.5us

0 1 0 0

25us

0 1 0 1

50us

0 1 1 0

75us

0 1 1 1

100us

1 0 0 0

125us

1 0 0 1

150us

1 0 1 0

175us

1 0 1 1

200us

1 1 0 0

2250us

1 1 0 1

250us

1 1 1 0

275us

1 1 1 1

300us

4.8 Flow Control Threshold Register ( 09H )

Bit

Name

Default

Description

7:4

HWOT

PHS3h, RW

RX FIFO High Water Overflow Threshold

Send a pause packet with pause_time=FFFFH when the RX RAM free space is

less than this value., If this value is zero, its meaning is no free RX SARM space.

Default is 3K-byte free space. Please don’t exceed SRAM size.

(1 unit=1K bytes)

3:0

LWOT

PHS8h, RW

RX FIFO Low Water Overflow Threshold

Send a pause packet with pause_time=0000 when RX SARM free space is

larger than this value. This pause packet is enabled after high water pause

packet transmitted. Default SRAM free space is 8K-byte. Please don’t exceed

SRAM size.

(1 unit=1K bytes)

DM9621 Datasheet(PDF) 18 Page - Davicom Semiconductor, Inc.

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