DM9621 datasheet(20/66 Pages) DAVICOM

20 / 66 page

DM9621

USB2.0 to Fast Ethernet Controller

Preliminary

Version: DM9621 -14-DS-P02

February 23, 2011

ERRE

PH0,RO

EEPROM Access Status or PHY Access Status

When set, it indicates that the EEPROM or PHY access is in progress.

4.11 EEPROM & PHY Address Register ( 0CH )

Bit

Name

Default

Description

7:6

PHY_ADR

PH01,RW PHY Address bit [1:0] or EEPROM Word Address[7:6]:

If it is in PHY mode operation , the PHY address bit [4:2] is force to 0.

Force to 01 if internal PHY is selected.

Or EEPROM Word Address[7:6] if EEPROM 93C56/66 is used

5:0

EROA

PH0,RW

EEPROM Word Address[5:0] or PHY Register Number

4.12 EEPROM & PHY Data Register (

EE_PHY_L：0DH

EE_PHY_H：0EH

)

Bit

Name

Default

Description

7:0

EE_PHY_L

X,RW

EEPROM or PHY Low Byte Data

7:0

EE_PHY_H

X,RW

EEPROM or PHY High Byte Data

4.13 Wake Up Control Register ( 0FH )

Bit

Name

Type

Description

SMI_EN

P0,RW

SMI_C Event Enable

When set, enable SMI_C as GPIO Wake-up Event.

This event occurred in 100ms low state and then 100ms high state in SMI_C pin

SMI_ST

P0,RO

SMI_C Even Status

When set, indicates SMI_C Event occurred.

LINKEN

PE0,RW

Link Change Event Enable

When set, enable Link Status Change Wake-up Event.

SAMPLEEN

PE0,RW

Sample Frame Match Event Enable

When set, enable Sample Frame Wake-up Event.

MAGICEN

PE0,RW

Magic Packet Event Enable

When set, enable Magic Packet Wake-up Event.

LINKST

P0,RO

Link change Event Status

When set, indicates link change and Link Status Change Event occurred.

SAMPLEST

P0,RO

Sample Frame Mtach Event Status

When set, indicates the sample frame is received and Sample Frame Event

occurred. This bit will not be affected after a software reset.

MAGICST

P0,RO

Magic Packet Event Status

When set, indicates the Magic Packet is received and Magic packet Event

occurred. This bit will not be affected after a software reset.

4.14 Physical Address Register ( 10H~15H )

Bit

Name

Default

Description

7:0

PAB5

E,RW

Physical Address Byte 5 (15H)

7:0

PAB4

E,RW

Physical Address Byte 4 (14H)

7:0

PAB3

E,RW

Physical Address Byte 3 (13H)

7:0

PAB2

E,RW

Physical Address Byte 2 (12H)

7:0

PAB1

E,RW

Physical Address Byte 1 (11H)

7:0

PAB0

E,RW

Physical Address Byte 0 (10H)

DM9621 Datasheet(PDF) 20 Page - Davicom Semiconductor, Inc.

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