DM9621 datasheet(52/66 Pages) DAVICOM

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DM9621

USB2.0 to Fast Ethernet Controller

Preliminary

Version: DM9621 -14-DS-P02

February 23, 2011

7.2.10 100Base-TX Receiver

The 100Base-TX receiver contains several function

blocks that convert the scrambled 125Mb/s serial

data to synchronous 4-bit nibble data that is then

provided to the MII.

The receive section contains the following functional

blocks:

- Signal Detect

- Digital Adaptive Equalization

- MLT-3 to Binary Decoder

- Clock Recovery Module

- NRZI to NRZ Decoder

- Serial to Parallel

- Descrambler

- Code Group Alignment

- 4B5B Decoder

7.2.11 Signal Detect

The signal detect function meets the specifications

mandated by the ANSI XT12 TP-PMD 100Base-TX

Standards for both voltage thresholds and timing

parameters.

7.2.12 Adaptive Equalization

When transmitting data at high speeds over copper

twisted pair cable, attenuation based on frequency

becomes a concern. In high speed twisted pair

signaling, the frequency content of the transmitted

signal can vary greatly during normal operation based

on the randomness of the scrambled data stream.

This variation in signal attenuation caused by

frequency variations must be compensated for to

ensure the integrity of the received data. In order to

ensure quality transmission when employing MLT-3

encoding, the compensation must be able to adapt to

various cable lengths and cable types depending on

the installed environment. The selection of long cable

lengths for a given implementation, requires

significant compensation which will be over-kill in a

situation that includes shorter, less attenuating cable

lengths. Conversely, the selection of short or

intermediate cable lengths requiring less

compensation will cause serious under-compensation

for longer length cables. Therefore, the compensation

or equalization must be adaptive to ensure proper

conditioning of the received signal independent of the

cable length.

7.2.13 MLT-3 to NRZI Decoder

The DM9621 decodes the MLT-3 information from

the Digital Adaptive Equalizer into NRZI data. The

relationship between NRZI and MLT-3 data is shown

in figure 4.

7.2.14 Clock Recovery Module

The Clock Recovery Module accepts NRZI data from

the MLT-3 to NRZI decoder. The Clock Recovery

Module locks onto the data stream and extracts the

125Mhz reference clock. The extracted and

synchronized clock and data are presented to the

NRZI to NRZ Decoder.

7.2.15 NRZI to NRZ

The transmit data stream is required to be NRZI

encoded in for compatibility with the TP-PMD

standard for 100Base-TX transmission over

Category-5 unshielded twisted pair cable. This

conversion process must be reversed on the receive

end. The NRZI to NRZ decoder, receives the NRZI

data stream from the Clock Recovery Module and

converts it to a NRZ data stream to be presented to

the Serial to Parallel conversion block.

7.2.16 Serial to Parallel

The Serial to Parallel Converter receives a serial data

stream from the NRZI to NRZ converter, and converts

the data stream to parallel data to be presented to the

descrambler.

7.2.17 Descrambler

Because of the scrambling process required to

control the radiated emissions of transmit data

streams, the receiver must descramble the receive

data streams. The descrambler receives scrambled

parallel data streams from the Serial to Parallel

converter, descrambles the data streams, and

presents the data streams to the Code Group

alignment block.

DM9621 Datasheet(PDF) 52 Page - Davicom Semiconductor, Inc.

DM9621 Datasheet(HTML) 52 Page - Davicom Semiconductor, Inc.

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