DM9621 datasheet(31/66 Pages) DAVICOM

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DM9621

USB2.0 to Fast Ethernet Controller

Preliminary

Version: DM9621 -14-DS-P02

February 23, 2011

Jabber detect

0,RO/LH

Jabber detect:

1 = Jabber condition detected

0 = No jabber

This bit is implemented with a latching function. Jabber conditions

will set this bit unless it is cleared by a read to this register through a

management interface or a PHY reset. This bit works only in

10Mbps mode

Extended

capability

1,RO/P

Extended capability:

1 = Extended register capable

0 = Basic register capable only

6.3 PHY ID Identifier Register #1 (PHYID1) – 02H

The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9621. The Identifier consists

of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model

revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.

Bit

Bit Name

Default

Description

15.0

OUI_MSB

<0181h>

OUI most significant bits:

This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of

this register respectively. The most significant two bits of the OUI

are ignored (the IEEE standard refers to these as bit 1 and 2)

6.4 PHY Identifier Register #2 (PHYID2) – 03H

Bit

Bit Name

Default

Description

15-10

OUI_LSB

<101110>,

RO/P

OUI least significant bits:

Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this

9-4

VNDR_MDL

<001011>,

RO/P

Vendor model number:

Six bits of vendor model number mapped to bit 9 to 4 (most

significant bit to bit 9)

3-0

MDL_REV

<0000>,

RO/P

Model revision number:

Four bits of vendor model revision number mapped to bit 3 to 0

(most significant bit to bit 3)

6.5 Auto-negotiation Advertisement Register(ANAR) – 04H

This register contains the advertised abilities of this DM9621 device as they will be transmitted to its link partner

during Auto-negotiation.

Bit

Bit Name

Default

Description

0,RO/P

Next page indication:

0 = No next page available

1 = Next page available

The PHY has no next page, so this bit is permanently set to 0

ACK

0,RO

Acknowledge:

1 = Link partner ability data reception acknowledged

0 = Not acknowledged

The PHY's auto-negotiation state machine will automatically

control this bit in the outgoing FLP bursts and set it at the

appropriate time during the auto-negotiation process. Software

should not attempt to write to this bit.

DM9621 Datasheet(PDF) 31 Page - Davicom Semiconductor, Inc.

DM9621 Datasheet(HTML) 31 Page - Davicom Semiconductor, Inc.

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