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DM9621 Datasheet(PDF) 36 Page - Davicom Semiconductor, Inc. |
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DM9621 Datasheet(HTML) 36 Page - Davicom Semiconductor, Inc. |
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36 / 66 page  DM9621 USB2.0 to Fast Ethernet Controller Preliminary 36 Version: DM9621 -14-DS-P02 February 23, 2011 6.10 10BASE-T Configuration/Status (10BTCSR) – 12H Bit Bit Name Default Description 15 RESERVED 0, RO Reserved: Write as 0, ignore on read 14 LP_EN 1, RW Link pulse enable: 1 = Transmission of link pulses enabled 0 = Link pulses disabled, good link condition forced This bit is valid only in 10Mbps operation. 13 HBE 1,RW Heartbeat enable: 1 = Heartbeat function enabled 0 = Heartbeat function disabled When the PHY is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode). 12 SQUELCH 1, RW Squelch enable : 1 = normal squelch 0 = low squelch 11 JABEN 1, RW Jabber Enable: Enables or disables the Jabber function when the PHY is in 10BASE-T full duplex or 10BASE-T transceiver loopback mode 1 = Jabber function enabled 0 = Jabber function disabled 10-1 RESERVED 0, RO Reserved: Write as 0, ignore on read 0 POLR 0, RO Polarity reversed: When this bit is set to 1, it indicates that the 10Mbps cable polarity is reversed. This bit is set and cleared by 10BASE-T module automatically. 6.11 Power down Control Register (PWDOR) – 13H Bit Bit Name Default Description 15 -9 Reserved 0, RO Reserved Read as 0, ignore on write 8 PD10DRV 0, RW Vendor power down control test 7 PD100DL 0, RW Vendor power down control test 6 PDchip 0, RW Vendor power down control test 5 PDcom 0, RW Vendor power down control test 4 PDaeq 0, RW Vendor power down control test 3 PDdrv 0, RW Vendor power down control test 2 PDedi 0, RW Vendor power down control test 1 PDedo 0, RW Vendor power down control test 0 PD10 0, RW Vendor power down control test * When selected, the power down value is control by Register 14H |
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