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DM9621 Datasheet(PDF) 21 Page - Davicom Semiconductor, Inc.

Part # DM9621
Description  USB2.0 to 10/100M Fast Ethernet Controller
PDF  66 Pages
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Manufacturer  DAVICOM [Davicom Semiconductor, Inc.]
Direct Link  http://www.davicom.com.tw
Logo DAVICOM - Davicom Semiconductor, Inc.

DM9621 Datasheet(HTML) 21 Page - Davicom Semiconductor, Inc.

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DM9621
USB2.0 to Fast Ethernet Controller
Preliminary
21
Version: DM9621 -14-DS-P02
February 23, 2011
4.15 Multicast Address Register ( 16H~1DH )
Bit
Name
Default
Description
7:0
MAB7
P80,RW
Multicast Address Byte 7 (1DH)
7:0
MAB6
P00,RW
Multicast Address Byte 6 (1CH)
7:0
MAB5
P00,RW
Multicast Address Byte 5 (1BH)
7:0
MAB4
P00,RW
Multicast Address Byte 4 (1AH)
7:0
MAB3
P00,RW
Multicast Address Byte 3 (19H)
7:0
MAB2
P00,RW
Multicast Address Byte 2 (18H)
7:0
MAB1
P00,RW
Multicast Address Byte 1 (17H)
7:0
MAB0
P00RW
Multicast Address Byte 0 (16H)
4.16 General purpose control Register
( 1EH )
Bit
Name
Default
Description
7:4
RESERVED
P0,RO
Reserved
3:0
RESERVED
P0111,RW
Reserved
4.17 General purpose Register ( 1FH )
Bit
Name
Default
Description
7:4
RESERVED
P0,RO
Reserved
3:1
RESERVED
P0,RW
Reserved
0
GEPIO0
PE1,RW
General purpose :
When the correspondent bit of General Purpose Control Register is 1, the value
of the bit is output to pin GEPIO0.
When the correspondent bit of General Purpose Control Register is 0, the value
of the bit be read is reflected from pin GEPIO0.
GEPIO0 default output 1 to POWER_DOWN internal PHY. Driver need to clear
this POWER_DOWN signal by write “0” when it wants PHY active. If other
device need, it also can refer this signal. This default value can be programmed
by EEPROM. Please refer EEPROM description.
4.18 Vendor ID Register (28H~29H)
Bit
Name
Default
Description
7:0
VIDH
0AH,RO
Vendor ID high byte (29H)
7:0
VIDL
46H.RO
Vendor ID low byte (28H)
4.19 Product ID Register (2AH~2BH)
Bit
Name
Default
Description
7:0
PIDH
96H,R
Product ID high byte (2BH)
7:0
PIDL
20H.R
Product ID low byte (2AH)
4.20 Chip Revision Register (2CH)
Bit
Name
Default
Description
7:0
CHIPR
01H,RO
CHIP revision



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