DM9621 datasheet(22/66 Pages) DAVICOM

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DM9621

USB2.0 to Fast Ethernet Controller

Preliminary

Version: DM9621 -14-DS-P02

February 23, 2011

4.21 TX Special Control Register (2DH)

Bit

Name

Default

Description

RESERVED

PH0,RW

Reserved

LCOL_TRY

PH0,RW

Late Collision Retry

RESERVED

PH0,RW

Reserved

RESERVED

PH0,RW

Reserved

3:0

TX_GAP

PH0,RW

TX Inter frame Gap

0XXX: 96-bit

1000: 64-bit

1001: 72-bit

1010: 80-bit

1011: 88-bit

1100: 96-bit

1101: 104-bit

1110:112-bit

1111: 120-bit

4.22 External PHY Force Mode Control Register (2EH)

Bit

Name

Default

Description

7~6

RESERVED

0,RO

Reserved

EXTERNAL

HP0,RW

Force to external PHY mode

RESERVED

0,RO

Reserved

RESERVED

PH0,RW

Reserved

SPEED

HP0,RW

Force external PHY speed mode in MAC register 1 bit 7

0: force to 100Mbps mode

1: force to 10Mbps mode

DUPLEX

HP0,RW

Force external PHY duplex mode in MAC register 0 bit 3

0: force to full-duplex

1: force to half-duplex

LINK

HP0,RW

Force external PHY link mode in MAC register 1 bit 6

0: force to link ON

1: force to link OFF

4.23 Transmit Check Sum Control Register (31H)

Bit

Name

Default

Description

7~3

RESERVED

0,RO

Reserved

UDPCSE

HPS0,RW

UDP Checksum Generation Enable

TCPCSE

HPS0,RW

TCP Checksum Generation Enable

IPCSE

HPS0,RW

IP Checksum Generation Enable

DM9621 Datasheet(PDF) 22 Page - Davicom Semiconductor, Inc.

DM9621 Datasheet(HTML) 22 Page - Davicom Semiconductor, Inc.

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