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DM9621 Datasheet(PDF) 28 Page - Davicom Semiconductor, Inc. |
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DM9621 Datasheet(HTML) 28 Page - Davicom Semiconductor, Inc. |
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28 / 66 page  DM9621 USB2.0 to Fast Ethernet Controller Preliminary 28 Version: DM9621 -14-DS-P02 February 23, 2011 6. PHY Register Description ADD Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset Loop back Speed select Auto-N Enable Power Down Isolate Restart Auto-N Full Duplex Coll. Test Reserved 00H CONTR OL 0 0 1 1 0 0 0 1 0 000_0000 T4 Cap. TX FDX Cap. TX HDX Cap. 10 FDX Cap. 10 HDX Cap. Reserved Pream. Supr. Auto-N Compl. Remote Fault Auto-N Cap. Link Status Jabber Detect Extd Cap. 01H STATUS 0 1 1 1 1 0000 1 0 0 1 0 0 1 02H PHYID1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 PHYID2 1 0 1 1 1 0 Model No. Version No. 03H 01011 0000 04H Auto-Neg. Advertise Next Page FLP Rcv Ack Remote Fault Reserved FC Adv T4 Adv TX FDX Adv TX HDX Adv 10 FDX Adv 10 HDX Adv Advertised Protocol Selector Field 05H Link Part. Ability LP Next Page LP Ack LP RF Reserved LP FC LP T4 LP TX FDX LP TX HDX LP 10 FDX LP 10 HDX Link Partner Protocol Selector Field 06H Auto-Neg. Expansio n Reserved Pardet Fault LP Next Pg Able Next Pg Able New Pg Rcv LP AutoN Cap. 10H Specifie d Config. BP 4B5B BP SCR BP ALIGN BP_ADP OK Reserve dr TX Reserve d Reserve d Force 100LNK Reserve d Reserve d RPDCTR -EN Reset St. Mch Pream. Supr. Sleep mode Reserved 11H Specifie d Conf/Stat 100 FDX 100 HDX 10 FDX 10 HDX Reserve d Reverse d Reverse d PHY ADDR [4:0] Auto-N. Monitor Bit [3:0] 12H 10T Conf/Stat Rsvd LP Enable HBE Enable SQUE Enable JAB Enable Reserve d Reserved Polarity Reverse 13H PWDOR Reserved PD10DR V PD100l PDchip PDcrm PDaeq PDdrv PDecli PDeclo PD10 14H Specified config TSTSE1 TSTSE 2 FORCE_ TXSD FORCE_ FEF PREA MBLE X TX10M _PWR NWAY_ PWR Reserved MDIX_C NTL AutoNeg _dlpbk Mdix_fix Value Mdix_do wn MonSel1 MonSel0 Reserve d PD_valu e 1BH DSP_CT RL DSP Control 1DH PSCR Reversed PREA MBLEX AMPLIT UDE TX_PW R Reversed Key to Default In the register description that follows, the default column takes the form: <Reset Value>, <Access Type> / <Attribute(s)> Where： <Reset Value>: 1 Bit set to logic one 0 Bit set to logic zero X No default value (PIN#) Value latched in from pin # at reset <Access Type>: RO = Read only RW = Read/Write <Attribute (s)>: SC = Self clearing P = Value permanently set LL = Latching low LH = Latching high |
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