TLK3114SCZPV datasheet(16/68 Pages) TI1

16 / 68 page

2−4

Table 2−3. Parallel Data Terminals (Continued)

TERMINAL

XGMII

TYPE

DESCRIPTION

NAME

NUMBER

XGMII

NAME

TYPE

DESCRIPTION

TDA[0:7]

C8, B8, A8,

E9, D9, C9,

E10, D10

TXD[0:7]

HSTL/SST

L_2 input

Transmit data terminals, channel A. Parallel data on this bus is clocked on the rising

and falling edges of TCA.

TDA8

C10

TXC0

HSTL/SST

L_2 input

Transmit data/KGEN, channel A. When CODE is low, this terminal is the ninth bit of

an 8-b/10-b encoded byte to be transmitted. When CODE is high, this terminal acts

as the K-character generator indicator. When this terminal is high, it causes the data

on TDA(0−7) to be encoded into a K-character.

TDA9

B10

N/A

HSTL/SST

L_2 input

Transmit data terminal, channel A. When CODE is low, this terminal is the tenth bit

of an 8-b/10-b encoded byte. When CODE is high, this terminal is ignored.

TDB[0:7]

F13, F14,

F15, G13,

G15, G16,

H13, H15

TXD[8:15]

Transmit data terminals, channels B–D. When PSYNC is low, parallel data on this

TDC[0:7]

M13, M14,

M15, L13,

L15, L16, K13,

K15

TXD[16:23]

HSTL/SST

L_2 input

Transmit data terminals, channels B–D. When PSYNC is low, parallel data on this

bus is clocked on the rising and falling edges of the transmit channel clock (TCB,

TCC, TCD). When PSYNC is high, data on these buses is clocked on the rising and

falling edges of TCA.

TDD[0:7]

R8, T8, U8,

N9, P9, R9,

N10, P10

TXD[24:31]

TDB8

TDC8

TDD8

H16

K16

R10

TXC1

TXC2

TXC3

HSTL/SST

L_2 input

Transmit data/KGEN, channels B–D. When PSYNC is low, data on these terminals

is clocked on the rising and falling edges of the transmit channel clock (TCB, TCC,

or TCD). When PSYNC is high, data on these terminals is clocked on the rising and

falling edges of TCA.

When CODE is low, these terminals are the ninth bit of an 8-b/10-b encoded byte

to be transmitted. When CODE is high, these terminals act as the K-character

generator indicator. When driven high, these terminals cause the data on TDx(0−7)

to be encoded into a K-character.

TDB9

TDC9

TDD9

J13

J15

T10

N/A

HSTL/SST

L_2 input

Transmit data terminal, channels B–D. When PSYNC is low, data on these terminals

is clocked on the rising and falling edges of the transmit channel clock (TCB, TCC,

TCD). When PSYNC is high, data on these terminals is clocked on the rising and

falling edges of TCA.

When CODE is low, these terminals are the tenth bit of an 8-b/10-b encoded byte.

When CODE is high, these terminals are ignored.

Table 2−4. JTAG Test Port Interface

TERMINAL

TYPE

DESCRIPTION

NAME

NUMBER

TYPE

DESCRIPTION

TCLK

LVTTL input

JTAG clock. TCLK clocks state information and test data into and out of the device during the

operation of the test port.

TDI

LVTTL input†

JTAG input data. TDI serially shifts test data and test instructions into the device during the

operation of the test port.

TDO

LVTTL output

JTAG output data. TDO serially shifts test data and test instructions out of the device during

operation of the test port. When the JTAG port is not in use, TDO is in a high-impedance state.

TMS

LVTTL input†

JTAG mode select. TMS controls the state of the internal test-port controller.

† With an internal pullup resistor

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