TLK3114SCZPV datasheet(30/68 Pages) TI1

30 / 68 page

3−12

ALIGN—This is the normal state for receiving data. When in this state, the column state machine sets the column

alignment sync bit to 1 in MDIO registers 4.24 and 5.24, bit 12, indicating all channels are aligned. During this state,

the alignment character code detect circuit is active on each channel but the column re-alignment is disabled. If a

complete alignment column is not detected in the correct position within the IPG, the column state machine transitions

to state FAIL1.

FAIL1—When in this state, the column alignment sync bit is 1 in MDIO registers 4.24 and 5.24, bit 12. During this

state, the alignment character code detect circuit is active on each channel but the column re-alignment is disabled.

If a complete alignment column is not detected in the correct position within the IPG, the column state machine

transitions to state FAIL2.

FAIL2—When in this state, the column alignment sync bit is 1 in MDIO registers 4.24 and 5.24, bit 12. During this

state, the alignment character code detect circuit is active on each channel but the column re-alignment is disabled.

If a complete alignment column is not detected in the correct position within the IPG, the column state machine

transitions to state FAIL3.

FAIL3—When in this state, the column alignment sync bit is 1 in MDIO registers 4.24 and 5.24, bit 12. During this

state, the alignment character code detect circuit is active on each channel but the column re-alignment is disabled.

If complete alignment column is not detected in the correct position within the IPG, the column state machine

transitions to state UNALIGN.

3.17 Independent Channel Mode

When the TLK3114SC device is configured in independent channel mode, the recovered clocks for each channel are

used to output the received data on the parallel interface. Thus, as is shown in Figure 3−11, in the independent

channel modes, no FIFO is enabled.

Channel

Logic

Protocol Device

Channel A

RCA

TLK3114SC

Serdes

Core

Data A

Channel

Logic

Channel B

RCB

Data B

Serdes

Core

Channel

Logic

Channel C

RCC

Data C

Serdes

Core

Channel

Logic

Channel D

RCD

Data D

Serdes

Core

RCLKB

RCLKC

RCLKD

RCLKA

Xtal OSC

RFCP/RFCN

Figure 3−11. Receive and Reference Clock Relationship (Independent Channel Modes)

TLK3114SCZPV Datasheet(PDF) 30 Page - Texas Instruments

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