TLK3114SCZPV datasheet(31/68 Pages) TI1

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3−13

3.18 Inter-Packet Gap Management

When in the 10-Gbps ethernet XGXS operational mode, the TLK3114SC device replaces the idle codes (see

Table 3−5) during the IPG with the necessary codes to perform all channel alignment, byte alignment, and clock

tolerance compensation as defined in IEEE 802.3ae, subclause 48.2.4.2. According to clause 46, a valid packet must

begin on channel A. However, due to variable packet sizes, the IPG can begin on any channel. The TLK3114SC

device replaces idle codes latched on the same TCA (TX_CLK) clock edge as the end of packet code with /K/ codes

(as shown in Figure 3−12).

TDA[7:0]

Packet

...

IPG

TDB[7:0]

...

TDC[7:0]

...

TDD[7:0]

...

Input

TXA

...

TXB

...

TXC

...

TXD

...

Output

S = Start of Packet

D = Data

T = End of Packet

A = K28.3

K = K28.5

R = K28.0

I = Idle

Figure 3−12. Inter-Packet Gap Management

The subsequent idles in the IPG are replaced by columns of channel alignment codes (K28.3), byte alignment codes

(K28.5), or clock tolerance compensation codes (K28.0). The state machine, which governs the IPG replacement

procedure, is illustrated in Figure 3−13, with notation defined in Table 3−8. Note that any IPG management state

transitions to send data if the IPG is terminated.

The repetition of the A pattern on each serial channel allows the FIFOs to remove or add the required phase delay

to align the data from all four channels for output on a single edge of the receive clock for channel A, RCA, as shown

in Figure 3−14.

TLK3114SCZPV Datasheet(PDF) 31 Page - Texas Instruments

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