TLK3114SCZPV datasheet(36/68 Pages) TI1

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3−18

3.22 High-Speed VML Output Driver

The high-speed data output driver is implemented using voltage mode logic that offers PECL-compatible differential

pair for a 100-

Ω differential impedance environment with no external components. The line can be directly coupled

or ac coupled. See Figure 4−8 and Figure 4−9 for termination details.

Both current mode logic (CML) and PECL drivers require external components to provide a rising edge (CML) or a

falling edge (PECL). The disadvantage of the external edge control is a limited edge rate due to package and line

parasitics. In contrast, a VML driver drives and controls both the rising and falling edges inside the package and

therefore provides optimum performance for increased speed requirements. Furthermore, the VML driver controls

the output voltage swing and adjusts automatically for varying load conditions. The PECL-compatible output provides

a nominal 850-mV (singled-ended) swing centered at VDDA/2. The receiver input contains internal biasing for

ac-coupling. The receiver internal circuitry sets the common mode voltage to 2

× VDDA/3.

When transmitting data across long lengths of PCB trace or cable, the high frequency content of the signal is

attenuated due to the skin effect of the media. This causes a smearing of the data eye when viewed on an

oscilloscope. The net result is reduced timing margins for the receiver and clock recovery circuits. In order to provide

equalization for the high frequency loss, the differential swing is increased or preemphasized for the bit immediately

following a transition and subsequently reduced or deemphasized for run lengths greater than one, as shown in

Figure 3−17. This provides additional high frequency energy to compensate for PCB or cable loss. The level of the

preemphasis is programmable via bits 4 and 5 of MDIO registers 16−20. Users can control the strength of the

preemphasis to optimize for a specific system requirement. There are two control bits in the user-defined registers

of MDIO to set the preemphasis level, as shown in Table 3−9. See also Table 3−18 for MDIO settings.

Table 3−9. Programmable Preemphasis

PRE1 (Bit 4)

REGISTERS 16−20

PRE2 (Bit 5)

REGISTERS 16−20

PREEMPHASIS LEVEL

(VOD(p) / VOD(d)−1)†

30%

20%

10%

Preemphasis disabled

† VOD(p): Magnitude of the voltage swing when there is a transition in the data stream.

VOD(d): Magnitude of the voltage swing when there is no transition in the data stream.

VCMT

Bit

Time

Vod(p)

Vod(d)

Vod(p)

Vod(d)

Vod(pd) Vod(pp)

Bit

Time

Figure 3−17. Output Differential Voltage Under Preemphasis

3.23 Device Configuration

The TLK3114SC device has four operational configurations controlled by two configuration terminals, CONFIG0 and

CONFIG1. These configurations are listed in Table 3−10 and controlled by the MDIO interface (see Table 3−18).

When the device is put in a certain mode, unused circuit blocks are powered down to conserve the system power.

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