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TLK3114SCZPV Datasheet(PDF) 43 Page - Texas Instruments |
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TLK3114SCZPV Datasheet(HTML) 43 Page - Texas Instruments |
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43 / 68 page  3−25 Table 3−18. Global Configuration Register Bit Definitions (Register 16) BIT(S) NAME DESCRIPTION READ/WRITE 15 Reserved Read returns 0, writes are ignored. Read-only 14 De-skew state machine 1 = Enable deskew state machine described in Figure 3−10. 0 = Disable deskew state machine (default). Read/Write 13 Channel synchronization state machine 1 = Enable channel synchronization state machine described in Figure 3−7. 0 = Disable channel synchronization state machine (default). Read/Write 12 IPG management state machine 1 = Enable IPG management state machine described in Figure 3−13. 0 = Disable IPG management state machine (default). Read/Write 11 Clock tolerance compensation 1 = Enable clock tolerance compensation. 0 = Disable clock tolerance compensation (default). Read/Write 10:9 Multifunction pin output Multifunction (MF[A−D]) terminal configuration. Bit 10 Bit 9 Output 0 0 HSTL = 1, SSTL_2 = 0 (default) 0 1 1 = Comma detected, 0 = data 1 0 Register 22, bits 3−0 (LOS) 1 1 Register 22, bits 7−4 (PRBS pass) Read/Write 8 Loss of signal detection 1 = Enable LOS condition described in Table 3−6 for all channels (default). 0 = Disable this function. Read/Write 7 Configuration: Config1 Configuration bits (see Table 3−10), default value = 0. When CONFIG1 = low, this bit can be set to 1. When CONFIG1 = high, this bit is read-only. Logically ORed with external input CONFIG1. Read/Write 6 Configuration: Config0 Configuration bits (see Table 3−10), default value = 0 When CONFIG0 = low, this bit can be set to 1. When CONFIG0 = high, this bit is read-only. Logically ORed with external input CONFIG0. Read/Write 5 Preemphasis: Pre2 Programmable preemphasis control (see Table 3−9), default value = 0. Read/Write 4 Preemphasis: Pre1 Programmable preemphasis control (see Table 3−9), default value = 0. Read/Write 3 Reserved Read returns a 0, writes are ignored. Read-only 2 PRBS enable 1 = Enable PRBS internal generation and verification on all channels 0 = Normal operation (default). When PRBSEN = low, this bit can be set to 1. When PRBSEN = high, this bit is read-only. Logically ORed with PRBSEN. Read/Write 1 Comma detect enable 1 = Enable K28.5 code detection and bit alignment on all channels (default). 0 = Disable K28.5 code detection on all channels. Logically AND’ed with SYNCEN. Read/Write 0 Reserved Read returns a 0, writes are ignored. Read/Write |
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