TLK3114SCZPV datasheet(38/68 Pages) TI1

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3−20

3.25 MDIO Management Interface

The TLK3114SC device supports the MDIO interface as defined in clauses 22 and 45 of the IEEE 802.3ae Ethernet

specification. The MDIO allows register-based management and control of the serial links. Normal operation of the

TLK3114SC device is possible without use of this interface since all of the essential signals necessary for operations

are accessible via the device terminals. However, some additional features are accessible only through the MDIO.

The MDIO management interface consists of a bidirectional data path (MDIO) and a clock reference (MDC). The

timing required to read from the internal registers 0−31 is shown in Figure 3−19. The timing required to write to the

internal registers 0−31 is shown in Figure 3−20. The port address is defined by the external inputs PADR(0−4).

MDC

MDIO

Hi-Z

D15

32 “1”s

Preamble

SFD

Read Code

PHY Address

Turn Around

Data

Idle

Figure 3−19. Management Interface Read Timing

MDC

MDIO

D15

32 “1”s

Preamble

SFD

Write Code

PHY Address

Turn Around

Data

Idle

Figure 3−20. Management Interface Write Timing

The extended register address space transactions are orthogonal to register 0−31 transactions, distinguished by the

ST bytes. Extended address space registers are denoted X.Y, where X designates the device address and Y

designates the register number. The permitted device addresses are shown in Table 3−11. The DADR0 bit is defined

by an external input, while the DADR[4:1] bits are predetermined. Write transactions that address an invalid register

or device or a read-only register are ignored. Read transactions that address an invalid register return a 0. Read

transactions that address an invalid device are ignored.

Timing for an address transaction is shown in Figure 3−21. The timing required to write to the internal registers is

shown in Figure 3−22. The timing required to read from the internal registers is shown in Figure 3−23. The timing

required to read from the internal registers and then increment the active address for the next transaction is shown

in Figure 3−24.

Table 3−11. MDIO Device Address

DADR(4:1)

DADR0

DEVICE MODE

0010

PHY XS

0010

DTE XS

TLK3114SCZPV Datasheet(PDF) 38 Page - Texas Instruments

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