TLK3114SCZPV datasheet(59/68 Pages) TI1

59 / 68 page

4−3

4.7

HSTL Signals

See Chapter 2, Terminal Descriptions, for a list of HSTL signals.

NOTE:

For more information on HSTL specifications and test conditions, see EIA/JEDEC, High-Speed

Transceiver Logic (HSTL): A 1.5-V Output Buffer Supply Voltage Based Interface Standard for

Digital Integrated Circuits, EIA/JESD8-6, Aug 1995.

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

VOH(dc)

High-level output voltage

VDDQ−0.4

VDDQ

VOL(dc)

Low-level output voltage

0.4

VIH(dc)

High-level dc input voltage

DC input, logic high

Vref+0.1

VDDQ+0.3

VIL(dc)

Low-level dc input voltage

DC input, logic low

−0.3

Vref–0.1

VIH(ac)

High-level ac input voltage

AC input, logic high

Vref+0.2

VIL(ac)

Low-level ac input voltage

AC input, logic low

Vref–0.2

IOH(dc)

High output current

VDDQ = 1.5 V

−8

IOL(dc)

Low output current

VDDQ = 1.5 V

CIN

Input capacitance

4.8

Serial Transmitter/Receiver Characteristics

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

VOD(p)

TX output voltage magnitude away from common

Maximum preemphasis

enabled, See Figure 4−1

650

850

1000

VOD(d)

TX output voltage magnitude away from common

mode

Preemphasis disabled,

See Figure 4−1

600

800

VOD(pp)

TX output differential peak-to-peak voltage swing

Maximum preemphasis

enabled, See Figure 4−1

1300

1700

2000

mVP-P

VOD(pd)

TX output differential peak-to-peak voltage swing

Preemphasis disabled,

See Figure 4−1

1200

1450

1600

mVP-P

VCMT

TX output common mode voltage range

See Figure 4−1

1000

1250

1400

VID

RX input voltage magnitude away from common

mode

See Figure 4−3

100

1150

VID(p)

RX input differential peak-to-peak voltage swing

See Figure 4−3

200

2300

mVP-P

VCMR

RX input common mode voltage range

See Figure 4−3

1000

2000

ILKG

RX input leakage current

−10

µA

RX input capacitance

tr, tf

Differential output signal rise, fall time (20% to 80%)

RL = 50 Ω,

CL = 5 pF,

See Figure 4−1

130

JTOL

Jitter tolerance, total jitter at serial input

Zero crossing, See Figure 4−4

0.65

UI†

JDR

Serial input deterministic jitter

Zero crossing, See Figure 4−4

0.37

Serial input sinusoidal jitter <20 MHz

0.1

Serial output total jitter

PRBS at 3.125 GHz,

See Figure 4−2

0.2

0.35

Serial output deterministic jitter

PRBS at 3.125 GHz

0.17

R(LATENCY)

Total delay from RX input to RD output

See Figure 3−6

225

Bits

T(LATENCY)

Total delay from TD input to TX output

See Figure 3−2

120

Bits

† Unit interval (UI) is one serial bit time (320 ps minimum).

TLK3114SCZPV Datasheet(PDF) 59 Page - Texas Instruments

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