TLK3114SCZPV datasheet(23/68 Pages) TI1

23 / 68 page

3−5

Byte Received

RLatency

RXxP

RXxN

RDx[7:0]

RCLKx

10-Bit Code Received

Figure 3−6. Receiver Latency

3.10 Auto Detectable HSTL/SSTL_2 Class 1 I/O

The transmit and receive data buses of the TLK3114SC device are compatible with both high-speed transfer logic

(HSTL) supply and stub series terminated logic 2 (SSTL_2) Class 1 buffers. The TLK3114SC device determines

which buffer technology to use by sensing the voltage level on the VDDQ supply terminals at power up. If the voltage

on the VDDQ supply is between 2.3 V and 2.7 V, the TLK3114SC device provides the necessary drive current to meet

SSTL_2 Class 1 requirements. If the voltage on the VDDQ supply is between 1.4 V and 2 V, the TLK3114SC device

provides HSTL compatible signaling. During normal operation, the voltage level on the VDDQ terminals must not

change.

All HSTL/SSTL_2 Class 1 outputs are series terminated to provide direct connection to a 50-

Ω transmission line

signaling environment (see Figure 4−10 and Figure 4−11).

3.11 8-b/10-b Encoder

All true serial interfaces require a method of encoding to ensure sufficient transition density for the receiving PLL to

acquire and maintain lock. The encoding scheme also maintains the signal dc balance by keeping the number of 1s

and 0s the same, which allows for ac-coupled data transmission. The TLK3114SC device uses the 8-b/10-b encoding

algorithm that is used by fibre channel and gigabit ethernet. This provides good transition density for clock recovery

and improves error checking. The 8-b/10-b encoder/decoder function is enabled for all four channels by the assertion

of the CODE terminal. When enabled, the TLK3114SC device internally encodes and decodes the data such that the

user reads and writes actual 8-bit data on each channel.

When enabled, the 8-b/10-b encoder converts 8-bit wide data to a 10-bit wide encoded data character to improve

its transition density. This transmission code includes D-characters, used for transmitting data, and K-characters,

used for transmitting protocol information. Each K- or D-character code word can also have both a positive and a

negative disparity version. The disparity of a code word is selected by the encoder to balance the running disparity

of the serialized data stream.

The generation of K-characters to be transmitted on each channel is controlled by TDx8 (KGEN). When KGEN is

asserted along with the 8 bits of data TDx[0:7], an 8-b/10-b K-character is transmitted. Similarly, reception of

K-characters is reported by RDx8 (KFLAG). When KFLAG is asserted, the 8 bits of data on RDx[0:7] must be

interpreted as a K-character. The TLK3114SC device transmits and receives all 12 valid K-characters defined in

Table 3−4. Table 3−5 provides additional transmit data control coding and descriptions that have been proposed for

10 gigabits per second ethernet. Data patterns put on TDx[0:7], other than those defined in Table 3−4 when TDx8

is asserted, result in an invalid K-character being transmitted, which results in a code error at the receiver.

TLK3114SCZPV Datasheet(PDF) 23 Page - Texas Instruments