TLK3114SCZPV datasheet(37/68 Pages) TI1

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3−19

Table 3−10. Device Configuration

CONFIG0

CONFIG1

CONFIGURATION

Low

Full-duplex transceiver mode—normal operation (default after reset).

Low

High

Transmit-only mode—data on high-speed data inputs is ignored. Receive data bus is in a high-impedance state.

High

Low

Receive-only mode—high-speed data outputs are in a high-impedance state. Data on the transmit data bus is

ignored.

High

Repeater mode—recovered serial data and clock are sent back out the transmit serial output.

While transceiver, transmit-only, and receive-only modes are straightforward, the repeater mode of operation is

shown in Figure 3−18. The received serial data is recovered by the extracted clock and is then sent back out on the

transmit serial output. The data eye opens both vertically and horizontally.

Serializer

RXxP

RXxN

Recovered Clock

TXxP

TXxN

Deserializer

TX PLL

Mode

Selection

CONFIG0

CONFIG1

Repeater

Mode

Figure 3−18. Repeater-Mode Block Diagram

3.24 PRBS Generator

The TLK3114SC device has a built-in 27−1 PRBS self-test function available on each channel. The PRBS data pattern

represents a worst case data recovery task compared to any 8-b/10-b data pattern combination and is, therefore, a

sufficient test for the link and jitter tolerance. The self-test function is enabled by asserting the PRBSEN terminal or

setting bit 2 (PRBS enable) of MDIO channel configuration registers 16−20, 4.32768−4.32772, or 5.32768−5.32772.

When the self-test function is enabled, PRBS is generated and fed into the 10-bit parallel-to-serial converter input

the transmit circuitry as if it were normal data and sent out to the transmitter. The output can be sent to a BERT (bit

error rate tester), the receiver of another TLK3114SC channel, or can be looped back to the receive input of the same

channel. Since the PRBS is not really random but a predetermined sequence of 1s and 0s, the data can be captured

and checked for errors by a BERT.

Result reporting of the PRBS test (PRBS_PASS) is available on each receive channel multifunction (MF[A−D])

terminal. To enable the report of the PRBS tests, see bits 10 and 9 of MDIO register 16, 4.32768, or 5.32768. If

SYNCEN is high, then PRBS_PASS latches low on the first occurrence of a bit error. SYNCEN low releases the latch

function on PRBS_PASS. MDIO comma detect settings do not affect the latching function.

TLK3114SCZPV Datasheet(PDF) 37 Page - Texas Instruments

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