TLK3114SCZPV datasheet(29/68 Pages) TI1

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3−11

UNALIGN

FAIL3

FAIL2

||A||

Valid

Data

DET2

DET3

ALIGN

||A||

Valid

Data

FAIL1

Valid

Data

DET1

||A||

Valid

Data

Valid

Data

Valid

Data

De-skew

Error

||A||

De-skew

Error

De-skew

Error

De-skew

Error

De-skew

Error

RESET

or LOS

Valid

Data

De-skew

Error

De-skew

Error

Figure 3−10. Column De-skew State Machine

3.16.1 Column State Descriptions

UNALIGN—This is the initial state for the column state machine upon device power up or reset. If any of the channel

state machines are set to UNSYNC, the column state is set to UNALIGN. In this state, the column state machine

searches for alignment character codes (K28.3 or /A/) on each channel and aligns the FIFO pointers on each channel

to the /A/ character code. While in this state, the column alignment sync bit is set to 0 in MDIO registers 4.24 and 5.24,

bit 12, indicating the column is not aligned. The column state transitions to the DET1 state upon the detection and

alignment of /A/ character codes in all four channels.

NOTE: When the XGXS lane alignment bit equals 0, it causes a local fault to be output on the receive

data bus.

DET1—During this state, the alignment character code detect circuit is active on each channel but the column

re-alignment is disabled. The column state machine remains in this state looking for a column of alignment character

codes. If an incomplete alignment column is detected (alignment character codes not found on all channels), the

column state machine transitions to state UNALIGN. While in this state, the column alignment sync bit is set to 0 in

MDIO registers 4.24 and 5.24, bit 12, indicating the column is not aligned. Detection of a complete alignment column

causes the column state machine to transition to state DET2.

NOTE: When the XGXS lane alignment bit equals 0, it causes a local fault to be output on the receive

data bus.

DET2—During this state, the alignment character code detect circuit is active on each channel but the column

re-alignment is disabled. The column state machine remains in this state looking for a column of alignment character

codes. If an incomplete alignment column is detected (alignment character codes not found on all channels), the

column state machine transitions to state UNALIGN. While in this state, the column alignment sync bit is set to 0 in

MDIO registers 4.24 and 5.24, bit 12, indicating the column is not aligned. Detection of a complete alignment column

causes the column state machine to transition to state DET3.

NOTE: When the XGXS lane alignment bit equals 0, it causes a local fault to be output on the receive

data bus.

DET3—During this state, the alignment character code detect circuit is active on each channel but the column

re-alignment is disabled. The column state machine remains in this state looking for a column of alignment character

codes. If an incomplete alignment column is detected (alignment character codes not found on all channels), the

column state machine transitions to state UNALIGN. While in this state, the column alignment sync bit is set to 0 in

MDIO registers 4.24 and 5.24, bit 12, indicating the column is not aligned. Detection of a complete alignment column

causes the column state machine to transition to state ALIGN.

NOTE: When the XGXS lane alignment bit equals 0, it causes a local fault to be output on the receive

data bus.

TLK3114SCZPV Datasheet(PDF) 29 Page - Texas Instruments

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