TLK3114SCZPV datasheet(17/68 Pages) TI1

17 / 68 page

2−5

Table 2−5. Management Data Interface

TERMINAL

TYPE

DESCRIPTION

NAME

NUMBER

TYPE

DESCRIPTION

DADR0

LVTTL input

Management MMD address. DADR0 is the externally set device address, which configures PHY

XS or DTE XS according to Table 3−11.

MDC

LVTTL input

Management data clock. MDC is the clock reference for the transfer of management data to and

from the protocol device.

MDIO

LVTTL I/O

Management data I/O. MDIO is the bidirectional serial data path for the transfer of management

data to and from the protocol device.

PADR(0−4)

R1, T1,

T3, T2, R2

LVTTL input

Management PHY address. Device address PADR(0−4) is the externally set physical address

given to this device used to distinguish one device from another.

Table 2−6. Miscellaneous Terminals

TERMINAL

TYPE

DESCRIPTION

NAME

NUMBER

TYPE

DESCRIPTION

CODE

LVTTL input†

Encode enable. When CODE is high, the 8-b/10-b encoder and decoder is enabled.

CONFIG0

CONFIG1

C2, D2

LVTTL input‡

Configuration terminals. These terminals put the device under one of the three operation modes:

00 = Transceiver mode

01 = Transmit-only mode

10 = Receive-only mode

11 = Repeater mode

ENABLE

LVTTL input†

Standby enable. When this terminal is held low, the device is in a low-power state. When high, the

device operates normally.

LPEN(A−D)

C3, D3,

P3, R3

LVTTL input‡

Internal loop enable, channels A−D. When high, the serial output for each channel is internally

looped back to its serial input.

MF(A−D)

A16, B16,

T16, U16

LVTTL output

Multifunction outputs, channels A−D. The functions of these terminals are enabled via the MDIO.

Currently defined functions are:

Terminal indicates 1 for HSTL, 0 for SSTL_2 signaling (default),

LOS (loss of signal) for each channel,

COMMA_DET (K28.5 character detected) for each channel, and

PRBS_STATUS (pseudorandom bit stream test status) for each channel.

PRBSEN

LVTTL input‡

PRBS enable. When this terminal is asserted high, the PRBS generator and comparator circuits

are inserted into the transmit and receive data paths on all channels. PRBS_PASS is indicated on

the MFx terminals once they are enabled using MDIO.

PSYNC

LVTTL input‡

Channel synchronization enable. When PSYNC is high, all transmit data is latched on the rising

and falling edges of TCA and all receive data is valid on the rising and falling edges of RCA.

RSTN

LVTTL input†

Chip reset (FIFO clear). Pulling this terminal low recenters the transmit skew buffers, receive

channel synchronization FIFOs, and resets MDIO flags.

SYNCEN

LVTTL input†

Comma detect enable. When this terminal is high, comma detection and byte alignment for all

channels are enabled.

TESTEN

LVTTL input‡

Test mode enable. This terminal is used for manufacturing test. This terminal must be left

unconnected or tied low.

† With an internal pullup resistor

‡ With an internal pulldown resistor

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