TLK3114SCZPV datasheet(19/68 Pages) TI1

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3−1

3 Detailed Description

The TLK3114SC device has four operational interface modes controlled by the states of terminals CODE and

PSYNC. These operational interface modes are listed in Table 3−1.

Table 3−1. Operational Interface Modes

CODE

PSYNC

DESCRIPTION

Low

Four independent serializer/deserializers (serdes)

Low

High

Four synchronized serdes

High

Low

Four independent transceivers with on-chip 8-b/10-b encode/decode

High

10-gigabit ethernet XGMII extended sublayer (XGXS) transceiver

3.1

Serdes Modes

When CODE is deasserted, the TLK3114SC device performs serialization and deserialization of encoded data across

four ten-bit interfaces (TBI) similar to that done in fibre channel and 802.3z gigabit ethernet serdes devices. The

channels can be synchronized to allow use of one transmit data clock and one receive data clock.

3.2

10-Gbps Ethernet Transceiver Modes

When CODE and PSYNC are asserted, the TLK3114SC device supports the 32-bit data path, 4-bit control, 10-gigabit

media independent interface (XGMII), and full encoding scheme specified in the IEEE 802.3ae 10-Gigabit Ethernet

standard. In these modes, the TLK3114SC device performs the serialization/deserialization and channel

synchronization function of an extended auxiliary unit interface (XAUI), also specified in the IEEE 802.3ae 10-Gigabit

Ethernet standard.

3.3

Parallel Interface Clocking

Two clocking choices are selectable via the PSYNC terminal detailed in Table 3−2. Under channel sync mode

(PSYNC is high), TCA is used as the transmit data clock for all four channels. Under independent channel mode

(PSYNC is low), each channel uses its own transmit data clock (TCA−TCD) to latch data into the TLK3114SC device.

A data FIFO is placed in the transmit data path to resolve any phase difference between the transmit data clocks and

differential reference clock, RFCP/N.

Table 3−2. Parallel Interface Clocking Modes

PSYNC

PARALLEL INTERFACE CLOCKING OPERATION

Low

Independent channel mode. TC[A−D]/RC[A−D] clock in/out each individual channel

High

Channel sync mode. TCA/RCA clock in/out all channels of data

On the receive data path, in independent channel mode, the data for each channel is output referenced to each

channel’s extracted receive clock. In channel sync mode, the data on all channels are synchronized and output

referenced to the extracted receive clock for channel A, RCA. A FIFO is enabled in the parallel receive data path on

each channel to compensate for channel skew and clock phase tolerance differences between the recovered clocks

for each channel and the receive output clock, RCA. This FIFO has a total depth of 11 bytes.

3.4

Parallel Interface Data

Two data mode choices are selectable via the CODE terminal detailed in Table 3−3. In serdes mode, the transmit

data bus for each channel accepts 10-bit wide 8-b/10-b encoded data at the TDx[0:9] terminals. Data is latched on

the rising and falling edge of the transmit data clock. The 8-b/10-b encoded data is then phase aligned to the reference

clock (RFCP/RFCN), serialized, then transmitted sequentially beginning with bit 0 (TDx0) over the differential

high-speed serial transmit terminals.

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