TLK3114SCZPV datasheet(61/68 Pages) TI1

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4−5

4.9

SSTL_2 Class 1/HSTL Output Switching Characteristics

These characteristics are over recommended operating conditions unless otherwise noted.

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

tsu

RDx[0:9] setup prior to RCx transition high or low

See Figure 4−5, timing relative to 0.5xVDDQ

960

RDx[0:9] hold after RCx transition high or low

See Figure 4−5, timing relative to 0.5xVDDQ

960

slew

RDx[0:9] slew rate

CL = 10 pF

mV/ps

tsu

RCA, RCB,

RCC, RCD

RDx[9:0]

VDDQ/2

Figure 4−5. SSTL_2 Class 1/HSTL Output Timing Requirements

4.10 SSTL_2 Class 1/HSTL Input Timing Requirements

These characteristics are over recommended operating conditions unless otherwise noted.

PARAMETER

TEST CONDITION

MIN†

TYP

MAX

UNIT

tsu

TDx[0:9] setup prior to TCx transition high or low

See Figure 4−6, timing relative to VREF

480

TDx[0:9] hold after TCx transition high or low

See Figure 4−6, timing relative to VREF

480

† All values are at 25_C with a nominal supply.

tsu

TCA, TCB,

TCC, TCD

TDx[9:0]

VREF

Figure 4−6. SSTL_2 Class 1/HSTL Data Input Timing Requirements

TLK3114SCZPV Datasheet(PDF) 61 Page - Texas Instruments

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