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WM8946ECS/R Datasheet(PDF) 119 Page - Wolfson Microelectronics plc |
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WM8946ECS/R Datasheet(HTML) 119 Page - Wolfson Microelectronics plc |
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119 / 175 page ![]() Production Data WM8946 w PD, July 2012, Rev 4.3 119 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 10:8 FLL_OUTDIV [2:0] 001 FOUT clock divider 000 = 2 001 = 4 010 = 8 011 = 16 100 = 32 101 = 64 110 = 128 111 = 256 (FOUT = FVCO / FLL_OUTDIV) 7:5 FLL_CTRL_RA TE[2:0] 000 Frequency of the FLL control block 000 = FVCO / 1 (Recommended value) 001 = FVCO / 2 010 = FVCO / 3 011 = FVCO / 4 100 = FVCO / 5 101 = FVCO / 6 110 = FVCO / 7 111 = FVCO / 8 Recommended that this register is not changed from default. 4:2 FLL_FRATIO [2:0] 000 FVCO clock divider 000 = 1 001 = 2 010 = 4 011 = 8 1XX = 16 000 recommended for FREF > 1MHz 100 recommended for FREF < 16kHz 011 recommended for all other cases 1 FLL_FRAC 1 Fractional enable 0 = Integer Mode 1 = Fractional Mode Integer mode offers reduced power consumption. Fractional mode offers best FLL performance, provided also that N.K is a non-integer value. 0 FLL_ENA 0 FLL Enable 0 = Disabled 1 = Enabled Register 08h FLL Control 1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R9 (09h) FLL Control 2 15:0 FLL_K[15:0] 0011_0001 _0010_011 1 Fractional multiply for FREF (MSB = 0.5) Register 09h FLL Control 2 |
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