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WM8946ECS/R Datasheet(PDF) 115 Page - Wolfson Microelectronics plc |
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WM8946ECS/R Datasheet(HTML) 115 Page - Wolfson Microelectronics plc |
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115 / 175 page  Production Data WM8946 w PD, July 2012, Rev 4.3 115 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 1 = Enable Mute 4 SPKL_MIX_MU TE 1 Left Speaker PGA Mixer Mute 0 = Disable Mute 1 = Enable Mute 3 SPKR_MIX_EN A 0 Right speaker output mixer enable 0 = Disabled 1 = Enabled 2 SPKL_MIX_EN A 0 Left speaker output mixer enable 0 = Disabled 1 = Enabled 1 DACR_ENA 0 Right DAC Enable 0 = Disabled 1 = Enabled DACR_ENA must be set to 1 when processing right channel data from the DAC or Digital Beep Generator. 0 DACL_ENA 0 Left DAC Enable 0 = Disabled 1 = Enabled DACR_ENA must be set to 1 when processing left channel data from the DAC or Digital Beep Generator. Register 03h Power management 2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R4 (04h) Audio Interface 15:14 DACDATA_PU LL[1:0] 00 DACDAT pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 13:12 FRAME_PULL [1:0] 00 LRCLK pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 11:10 BCLK_PULL [1:0] 00 BCLK pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 9 ADCR_SRC 1 Right Digital Audio interface source 0 = Left ADC data is output on right channel 1 = Right ADC data is output on right channel 8 ADCL_SRC 0 Left Digital Audio interface source 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel 7 DACR_SRC 1 Right DAC Data Source Select 0 = Right DAC outputs left interface data 1 = Right DAC outputs right interface data 6 DACL_SRC 0 Left DAC Data Source Select 0 = Left DAC outputs left interface data 1 = Left DAC outputs right interface data 5 BCLK_INV 0 BCLK Invert |
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