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WM8946ECS/R Datasheet(PDF) 113 Page - Wolfson Microelectronics plc |
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WM8946ECS/R Datasheet(HTML) 113 Page - Wolfson Microelectronics plc |
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113 / 175 page  Production Data WM8946 w PD, July 2012, Rev 4.3 113 REGISTER BITS BY ADDRESS The complete register map is shown below. The detailed description can be found in the relevant text of the device description. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R0 (00h) Software Reset/Chip ID 1 15:0 SW_RESET [15:0] 0110_0010 _0010_100 1 Writing to this register resets all registers to their default state. Reading from this register will indicate device family ID 6229h. Register 00h Software Reset/Chip ID 1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R1 (01h) Chip ID 2 3:0 CHIP_REV[3:0] 0000 Reading from this register will indicate the Revision ID. Register 01h Chip ID 2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R2 (02h) Power management 1 13 INPPGAR_EN A 0 Right Input PGA Enable 0 = Disabled 1 = Enabled 12 INPPGAL_ENA 0 Left Input PGA Enable 0 = Disabled 1 = Enabled 11 ADCR_ENA 0 Right ADC Enable 0 = Disabled 1 = Enabled ADCR_ENA must be set to 1 when processing right channel data from the ADC or Digital Microphone. 10 ADCL_ENA 0 Left ADC Enable 0 = Disabled 1 = Enabled ADCL_ENA must be set to 1 when processing left channel data from the ADC or Digital Microphone. 7 DMIC_ENA 0 Enables Digital Microphone mode 0 = Audio DSP input is from ADC 1 = Audio DSP input is from digital microphone interface When DMIC_ENA = 0, the Digital microphone clock (DMICCLK) is held low. 4 MICB_ENA 0 Microphone Bias Enable 0 = Disabled 1 = Enabled 3 BIAS_ENA 0 Master Bias Enable 0 = Disabled 1 = Enabled 2 VMID_BUF_EN A 0 VMID Buffer Enable. (The buffered VMID may be applied to disabled input and output pins.) 0 = Disabled 1 = Enabled |
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