WM8946ECSSLASHR datasheet(117/175 Pages) WOLFSON

117 / 175 page

Production Data

WM8946

PD, July 2012, Rev 4.3

117

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R6 (06h)

Clock Gen

control

OSC_CLK_EN

Oscillator Enable

0 = Disabled

1 = Enabled

This needs to be set when a timeout clock is required

for PGA zero cross or GPIO input detection

14:13

MCLK_PULL

[1:0]

MCLK pull-up / pull-down Enable

00 = no pull-up or pull-down

01 = pull-down

10 = pull-up

11 = reserved

CLKOUT_SEL

CLKOUT Source Select

0 = SYSCLK

1 = FLL or MCLK (set by SYSCLK_SRC register)

11:10

CLKOUT_DIV

[1:0]

CLKOUT Clock divider

00 = divide by 1

01 = divide by 2

10 = divide by 4

11 = divide by 8

SYSCLK_ENA

SYSCLK Enable

0 = Disabled

1 = Enabled

SYSCLK_SRC

SYSCLK Source Select

0 = MCLK

1 = FLL output

7:5

SYSCLK_DIV

[2:0]

000

SYSCLK Clock divider

(Sets the scaling for either the MCLK or FLL clock

output, depending on SYSCLK_SRC)

000 = divide by 1

001 = divide by 1.5

010 = divide by 2

011 = divide by 3

100 = divide by 4

101 = divide by 6

110 = divide by 8

111 = divide by 12

TOCLK_ENA

TOCLK Enabled

(Enables timeout clock for GPIO level detection, AMU,

and PGA zero cross timeout)

0 = Disabled

1 = Enabled

3:1

BCLK_DIV[2:0]

011

BCLK Frequency (Master mode)

000 = SYSCLK

001 = SYSCLK / 2

010 = SYSCLK / 4

011 = SYSCLK / 8

100 = SYSCLK / 16

101 = SYSCLK / 32

110 = reserved

111 = reserved

MSTR

Digital Audio Interface Mode select

0 = Slave mode

1 = Master mode

WM8946ECS/R Datasheet(PDF) 117 Page - Wolfson Microelectronics plc

WM8946ECS/R Datasheet(HTML) 117 Page - Wolfson Microelectronics plc

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