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ADV7181BBCPZ Datasheet(PDF) 40 Page - Analog Devices

Part # ADV7181BBCPZ
Description  Multiformat SDTV Video Decoder
PDF  96 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADV7181BBCPZ Datasheet(HTML) 40 Page - Analog Devices

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ADV7181B
Rev. 0 | Page 40 of 96
PF Polarity FIELD, Address 0x37 [3]
The polarity of the FIELD pin can be inverted using the PF bit.
FIELD pin can be inverted using the PF bit.
When PF is 0 (default), FIELD is active high.
When PF is 1, FIELD is active low.
OUTPUT
VIDEO
FIELD 1
FIELD 2
H
V
F
OUTPUT
VIDEO
H
V
F
525
1
2
3
4
5
6
7
8
9
10
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13
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20
21
22
NVBEG[4:0] = 0x5
NVBEG[4:0] = 0x5
NVEND[4:0] = 0x4
NVEND[4:0] = 0x4
NFTOG[4:0] = 0x3
NFTOG[4:0] = 0x3
*BT.656-4
REG 0x04, BIT 7 = 1
*BT.656-4
REG 0x04, BIT 7 = 1
*APPLIES IF NEMAVMODE = 0:
MUST BE MANUALLY SHIFTED IF NEWAVMODE = 1.
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Figure 20. NTSC Default (BT.656). The polarity of H, V, and F is embedded in the data.
NVBEG[4:0] = 0x0
NVEND[4:0] = 0x3
FIELD 1
OUTPUT
VIDEO
FIELD
OUTPUT
HS
OUTPUT
NFTOG[4:0] = 0x5
VS
OUTPUT
525
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
21
22
FIELD 2
OUTPUT
VIDEO
FIELD
OUTPUT
HS
OUTPUT
VS
OUTPUT
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NVBEG[4:0] = 0x0
NVEND[4:0] = 0x3
NFTOG[4:0] = 0x5
Figure 21. NTSC Typical VSync/Field Positions Using Register Writes in Table 54



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