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SPC564A80L7 Datasheet(PDF) 122 Page - STMicroelectronics |
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SPC564A80L7 Datasheet(HTML) 122 Page - STMicroelectronics |
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122 / 157 page  Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7 122/157 Doc ID 15399 Rev 9 3.17.4 External Bus Interface (EBI) and calibration bus interface timing Table 41. External Bus Interface maximum operating frequency Port Width Multiplexed Mode ADDR[12:15] Pin Usage ADDR[16:31] Pin Usage DATA[0:15] Pin Usage Max. Operating Frequency 16-bit Yes ADDR[12:15] GPIO ADDR[16:31] DATA[0:15] 66 MHz(1) 16-bit No ADDR[12:15] ADDR[16:31] DATA[0:15] 33 MHz(2),(3) 32-bit Yes ADDR[12:15] ADDR[16:31] DATA[16:31] DATA[0:15] 33 MHz(2),(3) 1. Set SIU_ECCR[EBDF] to divide by two or divide by four if the system frequency is greater than 66 MHz. 2. System Frequency must be 132 MHz and SIU_ECCR[EBDF] set to divide by four. 3. Pad restrictions limit the maximum operating frequency. Table 42. Calibration bus interface maximum operating frequency Port Width Multiplexed Mode CAL_ADDR[12:15] Pin Usage CAL_ADDR[16:30] Pin Usage CAL_DATA[0:15] Pin Usage Max. Operating Frequency 16-bit Yes GPIO GPIO CAL_ADDR[12:30] CAL_DATA[0:15] 66 MHz(1) 16-bit No CAL_ADDR[12:15] CAL_ADDR[16:30] CAL_DATA[0:15] 66 MHz(1) 32-bit Yes CAL_WE[2:3] CAL_DATA[31] CAL_ADDR[16:30] CAL_DATA[16:30] CAL_ADDR[0:15] CAL_DATA[0:15] 66 MHz(1) 1. Set SIU_ECCR[EBDF] to divide by two or divide by four if the system frequency is greater than 66 MHz Table 43. External bus interface (EBI) and calibration bus operation timing (1) # Symbol C Characteristic 66 MHz (ext. bus)(2) Unit Notes Min Max 1TC CC P CLKOUT Period 15.2 — ns Signals are measured at 50% VDDE. 2tCDC CC D CLKOUT duty cycle 45% 55% TC 3tCRT CC D CLKOUT rise time — (3) ns 4tCFT CC D CLKOUT fall time — (3) ns 5tCOH CC D CLKOUT Posedge to Output Signal Invalid or High Z(Hold Time) – ADDR[8:31] –CS[0:3] – DATA[0:31] –OE – RD_WR –TS –WE[0:3]/BE[0:3] 1.3 — ns |
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