SPC564A80L7 datasheet(128/157 Pages) STMICROELECTRONICS

128 / 157 page

Electrical characteristics

SPC564A74L7, SPC564A80B4, SPC564A80L7

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Doc ID 15399 Rev 9

9tSUI

Data Setup Time for Inputs

Master (MTFE = 0)

VDDEH=4.5–5.5 V

—

VDDEH=3–3.6 V

23.5

—

DSlave

2—

Master (MTFE = 1, CPHA =

0)(12)

8—

Master (MTFE = 1, CPHA = 1)

VDDEH=4.5–5.5 V

—

VDDEH=3–3.6 V

23.5

—

tHI

Data Hold Time for Inputs

Master (MTFE = 0)

-4

—

DSlave

—

Master (MTFE = 1,

CPHA = 0)(12)

—

Master (MTFE = 1, CPHA = 1)

-4

—

tSUO

Data Valid (after SCK edge)

Master (MTFE = 0)

VDDEH=4.5–5.5 V

—

VDDEH=3–3.6 V

—

6.3

Slave

VDDEH=4.5–5.5 V

—

VDDEH=3–3.6 V

—

Master (MTFE = 1, CPHA = 0)

—

Master (MTFE = 1, CPHA = 1)

VDDEH=4.5–5.5 V

—

VDDEH=3–3.6 V

—

6.3

tHO

Data Hold Time for Outputs

Master (MTFE = 0)

VDDEH=4.5–5.5 V

–5

—

VDDEH=3 –3.6 V

–7.5

—

DSlave

5.5

—

Master (MTFE = 1, CPHA = 0)

—

Master (MTFE = 1, CPHA = 1)

VDDEH=4.5–5.5 V

–5

—

VDDEH=3–3.6 V

–7.5

—

All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on medium-speed pads. DSPI signals using slow

pads have an additional delay based on the slew rate. DSPI timing is specified at VDDEH = 3to3.6 V and VDDEH =

4.5 to 5.5 V, TA =TL to TH, and CL = 50 pF with SRC = 0b11.

Data is verified at fSYS = 102 MHz and 153 MHz (100 MHz and 150 MHz + 2% frequency modulation).

Table 48.

DSPI timing(1),(2) (continued)

Symbol

Characteristic

Condition

Min.

Max.

Unit

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