SPC564A80L7 datasheet(127/157 Pages) STMICROELECTRONICS

127 / 157 page

SPC564A74L7, SPC564A80B4, SPC564A80L7

Electrical characteristics

Doc ID 15399 Rev 9

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3.17.7

eMIOS timing

3.17.8

DSPI timing

DSPI channel frequency support for the SPC564A80 MCU is shown in Table 47. Timing

specifications are in Table 48.

Table 46.

eMIOS timing(1)

Symbol

Characteristic

Min.

Value

Max.

Value

Unit

1tMIPW

eMIOS Input Pulse Width

—

tCYC

2tMOPW

eMIOS Output Pulse Width

—

tCYC

eMIOS timing specified at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V, TA = TL to TH, and CL = 50 pF

with SRC = 0b00.

Table 47.

DSPI channel frequency support

System

Clock (MHz)

DSPI Use

Mode

Max. Usable

Frequency

(MHz)

Notes

150

LVDS

37.5

Use sysclock /4 divide ratio.

Non-LVDS

18.75

Use sysclock /8 divide ratio.

120

LVDS

Use sysclock /3 divide ratio. Gives 33/66 duty cycle. Use DSPI

configuration DBR=0b1 (double baud rate), BR=0b0000

(scaler value 2) and PBR=0b01 (prescaler value 3).

Non-LVDS

Use sysclock /6 divide ratio.

LVDS

Use sysclock /2 divide ratio.

Non-LVDS

Use sysclock /4 divide ratio.

Table 48.

DSPI timing(1),(2)

Symbol

Characteristic

Condition

Min.

Max.

Unit

1tSCK

SCK Cycle Time(3),(4),(5)

24.4 ns

2.9 ms

—

2tCSC

PCS to SCK Delay(6)

22(7)

—ns

3tASC

After SCK Delay(8)

21(9)

—ns

4tSDC

SCK Duty Cycle

(

½tSC)–2

(

½tSC)+2

5tA

Slave Access Time

(SS active to SOUT driven)

—25

6tDIS

Slave SOUT Disable Time

(SS inactive to SOUT High-Z or

invalid)

—25

7tPCSC

PCSx to PCSS time

4(10)

—ns

8tPASC

PCSS to PCSx time

5(11)

—ns

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