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PLQP0048KB-B Datasheet(PDF) 63 Page - Renesas Technology Corp |
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PLQP0048KB-B Datasheet(HTML) 63 Page - Renesas Technology Corp |
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63 / 177 page  R01DS0261EJ0110 Rev.1.10 Page 63 of 177 Oct 30, 2015 RX230 Group, RX231 Group 4. I/O Registers 0008 AC4Ch SDHI Transfer Data Size Register SDSIZE 32 32 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 AC50h SDHI Card Access Option Register SDOPT 32 32 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 AC58h SDHI SD Error Status Register 1 SDERSTS1 32 32 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 AC5Ch SDHI SD Error Status Register 2 SDERSTS2 32 32 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 AC60h SDHI SD Buffer Register SDBUFR 32 32 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 AC68h SDHI SDIO Mode Control Register SDIOMD 32 32 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 AC6Ch SDHI SDIO Status Register SDIOSTS 32 32 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 AC70h SDHI SDIO Interrupt Mask Register SDIOIMSK 32 32 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 ADB0h SDHI DMA Transfer Enable Register SDDMAEN 32 32 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 ADC0h SDHI SDHI Software Reset Register SDRST 32 32 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 ADE0h SDHI Swap Control Register SDSWAP 32 32 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 B000h CAC CAC Control Register 0 CACR0 8 8 2 or 3 PCLKB 2 ICLK 0008 B001h CAC CAC Control Register 1 CACR1 8 8 2 or 3 PCLKB 2 ICLK 0008 B002h CAC CAC Control Register 2 CACR2 8 8 2 or 3 PCLKB 2 ICLK 0008 B003h CAC CAC Interrupt Request Enable Register CAICR 8 8 2 or 3 PCLKB 2 ICLK 0008 B004h CAC CAC Status Register CASTR 8 8 2 or 3 PCLKB 2 ICLK 0008 B006h CAC CAC Upper-Limit Value Setting Register CAULVR 16 16 2 or 3 PCLKB 2 ICLK 0008 B008h CAC CAC Lower-Limit Value Setting Register CALLVR 16 16 2 or 3 PCLKB 2 ICLK 0008 B00Ah CAC CAC Counter Buffer Register CACNTBR 16 16 2 or 3 PCLKB 2 ICLK 0008 B080h DOC DOC Control Register DOCR 8 8 2 or 3 PCLKB 2 ICLK 0008 B082h DOC DOC Data Input Register DODIR 16 16 2 or 3 PCLKB 2 ICLK Table 4.1 List of I/O Registers (Address Order) (21 / 42) Address Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access Cycles ICLK PCLK ICLK <PCLK |
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