HC08KL8GRSSLASHD datasheet(18/256 Pages) NXP

18 / 256 page

List of Figures

General Release Specification

MC68HC08KL8 — Rev. 2.0

List of Figures

Figure

Title

Page

8-10

Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

8-11

Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . .91

8-12

Interrupt Status Register 1 (INT1) . . . . . . . . . . . . . . . . . . . .93

8-13

Interrupt Status Register 2 (INT2) . . . . . . . . . . . . . . . . . . . .94

8-14

Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

8-15

Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . .97

8-16

Wait Recovery from Internal Reset . . . . . . . . . . . . . . . . . . .97

8-17

Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

8-18

Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . .98

8-19

Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . .99

8-20

Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . .101

8-21

Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . .102

9-1

USB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

9-2

Supported Transaction Types Per Endpoint . . . . . . . . . . .107

9-3

Supported USB Packet Types . . . . . . . . . . . . . . . . . . . . . .108

9-4

Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

9-5

SOP, Sync Signaling, and Voltage Levels . . . . . . . . . . . . .109

9-6

CRC Block Diagram for Token Packets . . . . . . . . . . . . . . .111

9-7

CRC Block Diagram for Data Packets . . . . . . . . . . . . . . . .112

9-8

EOP Transaction Voltage Levels . . . . . . . . . . . . . . . . . . . .113

9-9

EOP Width Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

9-10

External Low-Speed Device Configuration. . . . . . . . . . . . .117

9-11

Regulator Electrical Connections . . . . . . . . . . . . . . . . . . . .118

9-12

Regulator Bypass Option . . . . . . . . . . . . . . . . . . . . . . . . . .119

9-13

Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .121

9-14

Differential Input Sensitivity

Over Entire Common Mode Range . . . . . . . . . . . . . . . .121

9-15

Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

9-16

Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . . . .123

9-17

NRZI Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

9-18

Flow Diagram for NRZI. . . . . . . . . . . . . . . . . . . . . . . . . . . .125

9-19

Bit Stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

9-20

Flow Diagram for Bit Stuffing . . . . . . . . . . . . . . . . . . . . . . .127

9-21

9-22

USB Address Register (UADDR) . . . . . . . . . . . . . . . . . . . .131

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

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