HC08KL8GRSSLASHD datasheet(85/256 Pages) NXP

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System Integration Module (SIM)

Reset and System Initialization

MC68HC08KL8 — Rev. 2.0

General Release Specification

System Integration Module (SIM)

8.4.2.1 Power-On Reset

When power is first applied to the MCU, the power-on reset module

(POR) generates a pulse to indicate that power-on has occurred. The

external reset pin (RST) is held low while the SIM counter counts out

4096 CGMXCLK cycles. Sixty-four CGMXCLK cycles later, the CPU and

memories are released from reset to allow the reset vector sequence to

occur.

At power-on, these events occur:

•

A POR pulse is generated.

•

The internal reset signal is asserted.

•

The SIM enables the oscillator to drive CGMXCLK.

•

Internal clocks to the CPU and modules are held inactive for 4096

CGMXCLK cycles to allow stabilization of the oscillator.

•

The RST pin is driven low during the oscillator stabilization time.

•

The POR bit of the reset status register (RSR) is set and all other

bits in the register are cleared.

Figure 8-7. POR Recovery

PORRST

OSC1

CGMXCLK

CGMOUT

RST

IAB

4096

CYCLES

$FFFE

$FFFF

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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