HC08KL8GRSSLASHD datasheet(81/256 Pages) NXP

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System Integration Module (SIM)

SIM Bus Clock Control and Generation

MC68HC08KL8 — Rev. 2.0

General Release Specification

System Integration Module (SIM)

Table 8-1 shows the internal signal names used in this section.

8.3 SIM Bus Clock Control and Generation

The bus clock generator provides system clock signals for the CPU and

peripherals on the MCU. The system clocks are generated from an

incoming clock, CGMOUT, as shown in Figure 8-3.

Figure 8-3. SIM Clock Signals

Table 8-1. Signal Name Conventions

Signal Name

Description

CGMXCLK

Buffered OSC1 from the oscillator

CGMOUT

The CGMXCLK frequency divided by two. This signal is again

divided by two in the SIM to generate the internal bus clocks.

(Bus clock = CGMXCLK divided by four)

IAB

Internal address bus

IDB

Internal data bus

PORRST

Signal from the power-on reset module to the SIM

IRST

Internal reset signal

R/W

Read/write signal

÷ 2

BUS CLOCK

GENERATORS

SIM

SIM COUNTER

FROM

OSCILLATOR

FROM

OSCILLATOR

CGMOUT

CGMXCLK

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC08KL8GRS/D Datasheet(PDF) 81 Page - NXP Semiconductors

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