HC08KL8GRSSLASHD datasheet(82/256 Pages) NXP

82 / 256 page

System Integration Module (SIM)

General Release Specification

MC68HC08KL8 — Rev. 2.0

System Integration Module (SIM)

8.3.1 Bus Timing

In user mode, the internal bus frequency is the oscillator frequency

(CGMXCLK) divided by four.

8.3.2 Clock Startup from POR

When the power-on reset (POR) module generates a reset, the clocks

to the CPU and peripherals are inactive and held in an inactive phase

until after the 4096 CGMXCLK cycle POR timeout has completed. The

RST pin is driven low by the SIM during this entire period. The IBUS

clocks start upon completion of the timeout.

8.3.3 Clocks in Stop Mode and Wait Mode

Upon exit from stop mode by an interrupt, break, or reset, the SIM allows

CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do

not become active until after the stop delay timeout. This timeout is

selectable as 4096 or 32 CGMXCLK cycles. (See 8.7.2 Stop Mode.)

In wait mode, the CPU clocks are inactive. The SIM also produces two

sets of clocks for other modules. Refer to the wait mode subsection of

each module to see if the module is active or inactive in wait mode.

Some modules can be programmed to be active in wait mode.

8.4 Reset and System Initialization

The MCU has these reset sources:

•

Power-on reset module (POR)

•

External reset pin (RST)

•

Computer operating properly module (COP)

•

Illegal opcode

•

Illegal address

•

Universal serial bus module (USB)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC08KL8GRS/D Datasheet(PDF) 82 Page - NXP Semiconductors