HC08KL8GRSSLASHD datasheet(19/256 Pages) NXP

19 / 256 page

List of Figures

MC68HC08KL8 — Rev. 2.0

General Release Specification

List of Figures

Figure

Title

Page

9-23

USB Interrupt Register 0 (UIR0). . . . . . . . . . . . . . . . . . . . .132

9-24

USB Interrupt Register 1 (UIR1). . . . . . . . . . . . . . . . . . . . .134

9-25

USB Control Register 0 (UCR0) . . . . . . . . . . . . . . . . . . . . .136

9-26

USB Control Register 1 (UCR1) . . . . . . . . . . . . . . . . . . . . .138

9-27

USB Control Register 2 (UCR2) . . . . . . . . . . . . . . . . . . . . .140

9-28

USB Status Register (USR) . . . . . . . . . . . . . . . . . . . . . . . .142

9-29

USB Endpoint 0 Data Register (UE0D0–UE0D7) . . . . . . .143

9-30

USB Endpoint 1/Endpoint 2 Data Register

(UE1D0–UE1D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

9-31

OUT Token Data Flow for Receive Endpoint 0 . . . . . . . . .146

9-32

SETUP Token Data Flow for Receive Endpoint 0 . . . . . . .147

9-33

IN Token Data Flow for Transmit Endpoint 0 . . . . . . . . . . .148

9-34

IN Token Data Flow for Transmit

Endpoint 1/Endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . .149

10-1

Monitor Mode Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

10-2

Monitor Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

10-3

Break Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

10-4

Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

10-5

Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

10-6

Stack Pointer at Monitor Mode Entry . . . . . . . . . . . . . . . . .162

10-7

Monitor Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . .163

11-1

TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

11-2

TIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .168

11-3

PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . .172

11-4

TIM Status and Control Register (TSC) . . . . . . . . . . . . . . .179

11-5

TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . .181

11-6

TIM Counter Modulo Registers (TMODH:TMODL) . . . . . .182

11-7

TIM Channel Status and Control Registers

(TSC0:TSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

11-8

CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

11-9

TIM Channel Registers (TCH0H/L:TCH1H/L) . . . . . . . . . .187

12-1

I/O Port Register Summary . . . . . . . . . . . . . . . . . . . . . . . .190

12-2

Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . .192

Freescale Semiconductor, Inc.

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