HC08KL8GRSSLASHD datasheet(88/256 Pages) NXP

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System Integration Module (SIM)

General Release Specification

MC68HC08KL8 — Rev. 2.0

System Integration Module (SIM)

8.5.2 SIM Counter During Stop Mode Recovery

The SIM counter also is used for stop mode recovery. The STOP

instruction clears the SIM counter. After an interrupt, break, or reset, the

SIM senses the state of the short stop recovery bit, SSREC, in the mask

option register. If the SSREC bit is a logic 1, then the stop recovery is

reduced from the normal delay of 4096 CGMXCLK cycles down to 32

CGMXCLK cycles. This is ideal for applications using canned oscillators

that do not require long startup times from stop mode. External crystal

applications should use the full stop recovery time by having SSREC

cleared in the mask option register.

8.5.3 SIM Counter and Reset States

External reset has no effect on the SIM counter. (See 8.7.2 Stop Mode

for details.) The SIM counter is free-running after all reset states. (See

8.4.2 Active Resets from Internal Sources for counter control and

internal reset recovery sequences.)

8.6 Exception Control

Normal, sequential program execution can be changed in three different

ways:

•

Interrupts

–

Maskable hardware CPU interrupts

–

Non-maskable software interrupt instruction (SWI)

•

Reset

•

Break interrupts

8.6.1 Interrupts

An interrupt temporarily changes the sequence of program execution to

respond to a particular event. The flowchart in Figure 8-8 shows the

handling of system interrupts.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC08KL8GRS/D Datasheet(PDF) 88 Page - NXP Semiconductors