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HC08KL8GRS/D Datasheet(PDF) 78 Page - NXP Semiconductors

Part # HC08KL8GRS/D
Description  High-Performance M68HC08 Architecture
PDF  256 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

HC08KL8GRS/D Datasheet(HTML) 78 Page - NXP Semiconductors

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System Integration Module (SIM)
General Release Specification
MC68HC08KL8 — Rev. 2.0
System Integration Module (SIM)
8.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
8.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
8.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
8.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.8.1
Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.8.2
Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8.8.3
Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . .102
8.2 Introduction
This section describes the system integration module (SIM), which
supports up to 16 external and/or internal interrupts. Together with the
CPU, the SIM controls all MCU activities. The SIM is a system state
controller that coordinates CPU and exception timing. A block diagram
of the SIM is shown in Figure 8-1. Figure 8-2 is a summary of the SIM
I/O registers.
The SIM is responsible for:
•
Bus clock generation and control for CPU and peripherals
–
Stop/wait/reset/break entry and recovery
–
Internal clock control
•
Master reset control, including power-on reset (POR) and
computer operating properly (COP) timeout
•
Interrupt control:
–
Acknowledge timing
–
Arbitration control timing
–
Vector address generation
•
CPU enable/disable timing
•
Modular architecture expandable to 128 interrupt sources
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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