HC08KL8GRSSLASHD datasheet(71/256 Pages) NXP

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Central Processor Unit (CPU)

Opcode Map

MC68HC08KL8 — Rev. 2.0

General Release Specification

Central Processor Unit (CPU)

6.7 Opcode Map

See Table 6-2.

TAX

Transfer A to X

← (A)

– – – – – – INH

TPA

Transfer CCR to A

← (CCR)

– – – – – – INH

TST

opr

TSTA

TSTX

TST

opr,X

TST ,X

TST

opr,SP

Test for Negative or Zero

(A) – $00 or (X) – $00 or (M) – $00

0 – – ¤¤ –

DIR

INH

IX1

SP1

9E6D

TSX

Transfer SP to H:X

H:X

← (SP) + 1

– – – – – – INH

TXA

Transfer X to A

← (X)

– – – – – – INH

TXS

Transfer H:X to SP

(SP)

← (H:X) – 1

– – – – – – INH

Accumulator

Any bit

Carry/borrow bit

opr

Operand (one or two bytes)

CCR

Condition code register

Program counter

Direct address of operand

PCH Program counter high byte

dd rr

Direct address of operand and relative offset of branch instruction

PCL Program counter low byte

Direct to direct addressing mode

REL Relative addressing mode

DIR

Direct addressing mode

rel

Relative program counter offset byte

DIX+

Direct to indexed with post increment addressing mode

Relative program counter offset byte

ee ff

High and low bytes of offset in indexed, 16-bit offset addressing

SP1 Stack pointer, 8-bit offset addressing mode

EXT

Extended addressing mode

SP2 Stack pointer 16-bit offset addressing mode

Offset byte in indexed, 8-bit offset addressing

Stack pointer

Half-carry bit

Undeﬁned

Index register high byte

Overﬂow bit

hh ll

High and low bytes of operand address in extended addressing

Index register low byte

Interrupt mask

Zero bit

Immediate operand byte

Logical AND

IMD

Immediate source to direct destination addressing mode

Logical OR

IMM

Immediate addressing mode

⊕

Logical EXCLUSIVE OR

INH

Inherent addressing mode

( )

Contents of

Indexed, no offset addressing mode

–( )

Negation (two’s complement)

IX+

Indexed, no offset, post increment addressing mode

Immediate value

IX+D

Indexed with post increment to direct addressing mode

Sign extend

IX1

Indexed, 8-bit offset addressing mode

←

Loaded with

IX1+

Indexed, 8-bit offset, post increment addressing mode

IX2

Indexed, 16-bit offset addressing mode

Concatenated with

Memory location

Set or cleared

Negative bit

—

Not affected

Table 6-1. Instruction Set Summary (Continued)

Source

Form

Operation

Description

Effect on

CCR

VH I N Z C

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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