HC08KL8GRSSLASHD datasheet(92/256 Pages) NXP

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System Integration Module (SIM)

General Release Specification

MC68HC08KL8 — Rev. 2.0

System Integration Module (SIM)

8.6.1.2 SWI Instruction

The SWI instruction is a non-maskable instruction that causes an

interrupt regardless of the state of the interrupt mask (I bit) in the

condition code register.

NOTE:

A software interrupt pushes PC onto the stack. A software interrupt does

not push PC–1, as a hardware interrupt does.

8.6.2 Interrupt Status Registers

The flags in the interrupt status registers identify maskable interrupt

sources. Table 8-3 summarizes the interrupt sources and the interrupt

status register flags that they set. The interrupt status registers can be

useful for debugging.

Table 8-3. Interrupt Sources

Source

Flags

Mask(1)

INT Register Flag

Priority(2)

Vector Address

SWI Instruction

—

$FFFC–$FFFD

IRQ1 Pin

IRQF1

IMASK1

IF1

$FFFA–$FFFB

USB Endpoint 0 Transmit

TXD0F

TXD0IE

IF2

$FFF8–$FFF9

USB Endpoint 0 Receive

RXD0F

RXD0IE

USB Endpoint 1/

Endpoint 2 Transmit

TXD1F

TXD1IE

USB End of Packet

EOPF

EOPIE

USB Resume Interrupt

RESUMF

—

TIM Channel 0

CH0F

CH0IE

IF3

$FFF6–$FFF7

TIM Channel 1

CH1F

CH1IE

IF4

$FFF4–$FFF5

TIM Overﬂow

TOF

TOIE

IF5

$FFF2–$FFF3

Keyboard Pins

KEYF

IMASKK

IF6

$FFF0–$FFF1

1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction.

2. 0 = highest priority

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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