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HC08KL8GRS/D Datasheet(PDF) 113 Page - NXP Semiconductors |
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HC08KL8GRS/D Datasheet(HTML) 113 Page - NXP Semiconductors |
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113 / 256 page ![]() Universal Serial Bus Module (USB) Overview MC68HC08KL8 — Rev. 2.0 General Release Specification Universal Serial Bus Module (USB) 9.3.1.6 End-of-Packet (EOP) The single-ended 0 (SE0) state is used to signal an end-of-packet (EOP). The single-ended 0 state is indicated by both D+ and D– being below 0.8 V. EOP will be signaled by driving D+ and D– to the single- ended 0 state for two bit times followed by driving the lines to the idle state for one bit time. The transition from the single-ended 0 to the idle state defines the end of the packet. The idle state is asserted for one bit time and then both the D+ and D– output drivers are placed in their high- impedance state. The bus termination resistors hold the bus in the idle state. Figure 9-8 shows the data signaling and voltage levels for an end- of-packet transaction. Figure 9-8. EOP Transaction Voltage Levels The width of the SE0 in the EOP is about two bit times. The EOP width is measured with the same capacitive load used for maximum rise and fall times and is measured at the same level as the differential signal crossover points of the data lines. Figure 9-9. EOP Width Timing VOH (MIN) VSE (MAX) VSE (MIN) VOL (MAX) VSS BUS DRIVEN TO LAST BIT OF BUS IDLE EOP STROBE PACKET IDLE STATE BUS FLOATS EOP WIDTH tPeriod DIFFERENTIAL DATA LINES DATA CROSSOVER LEVEL Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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