AMD-K6-2ESLASH233AMZ datasheet(147/332 Pages) AMD

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Chapter 5

Signal Descriptions

129

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

5.54

WB/WT# (Writeback or Writethrough)

Pin Attribute

Input

Pin Location

AA-05

Summary

WB/WT#, together with PWT, specifies the data cache-line state

during cacheable read misses and write hits to shared cache

lines.

If WB/WT# = 0 or PWT = 1 during a cacheable read miss or

write hit to a shared cache line, the accessed line is cached

in the shared state. This is referred to as the writethrough

state, because all write cycles to this cache line are driven

externally on the bus.

If WB/WT# = 1 and PWT = 0 during a cacheable read miss or

a write hit to a shared cache line, the accessed line is cached

in the exclusive state. Subsequent write hits to the same line

cause its state to transition from exclusive to modified. This

is referred to as the writeback state, because the data cache

can contain modified cache lines that are subject to be

written back—referred to as a writeback cycle—as the result

of an inquire cycle, an internal snoop, a flush operation, or

the WBINVD instruction.

Sampled

WB/WT# is sampled on the clock edge on which the first BRDY#

or NA# of a bus cycle is sampled asserted. If the cycle is a burst

read, WB/WT# is ignored during the last three assertions of

BRDY #. WB /W T# is samp l e d d u r in g mem o ry re ad an d

non-writeback write cycles and is ignored during all other types

of cycles.

AMD-K6-2E/233AMZ Datasheet(PDF) 147 Page - Advanced Micro Devices