MC68HC908GR4MP datasheet(155/286 Pages) FREESCALE

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Port E

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

155

16.5.3 Port D Input Pullup Enable Register

The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each

of the seven port D pins. Each bit is individually configurable and requires that the data direction register,

DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port

bit’s DDRD is configured for output mode.

PTDPUE6–PTDPUE0 — Port D Input Pullup Enable Bits

These writeable bits are software programmable to enable pullup devices on an input port bit.

1 = Corresponding port D pin configured to have internal pullup

0 = Corresponding port D pin has internal pullup disconnected

16.6 Port E

Port E is a 2-bit special-function port that shares two of its pins with the serial communications interface

(SCI) module.

16.6.1 Port E Data Register

The port E data register contains a data latch for each of the two port E pins.

PTE1 and PTE0 — Port E Data Bits

PTE1 and PTE0 are read/write, software programmable bits. Data direction of each port E pin is under

the control of the corresponding bit in data direction register E.

NOTE

Data direction register E (DDRE) does not affect the data direction of port

E pins that are being used by the SCI module. However, the DDRE bits

always determine whether reading port E returns the states of the latches

or the states of the pins. See Table 16-6.

Address:

$000F

Bit 7

321

Bit 0

Read:

PTDPUE6

PTDPUE5

PTDPUE4

PTDPUE3

PTDPUE2

PTDPUE1

PTDPUE0

Write:

Reset:

000

= Unimplemented

Figure 16-16. Port D Input Pullup Enable Register (PTDPUE)

Address:

$0008

Bit 7

4321

Bit 0

Read:

000

PTE1

PTE0

Write:

Reset:

Unaffected by reset

Alternative Function:

RxD

TxD

= Unimplemented

Figure 16-17. Port E Data Register (PTE)

MC68HC908GR4MP Datasheet(PDF) 155 Page - Freescale Semiconductor, Inc

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