MC68HC908GR4MP datasheet(152/286 Pages) FREESCALE

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Input/Output Ports (I/O)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

152

Freescale Semiconductor

16.4.3 Port C Input Pullup Enable Register

The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each

of the two port C pins. Each bit is individually configurable and requires that the data direction register,

DDRC, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port

bit’s DDRC is configured for output mode.

PTCPUE1–PTCPUE0 — Port C Input Pullup Enable Bits

These writeable bits are software programmable to enable pullup devices on an input port bit.

1 = Corresponding port C pin configured to have internal pullup

0 = Corresponding port C pin internal pullup disconnected

16.5 Port D

Port D is an 7-bit special-function port that shares four of its pins with the serial peripheral interface (SPI)

module and three of its pins with two timer interface (TIM1 and TIM2) modules. Port D also has software

configurable pullup devices if configured as an input port.

16.5.1 Port D Data Register

The port D data register (PTD) contains a data latch for each of the seven port D pins.

PTD6–PTD0 — Port D Data Bits

These read/write bits are software-programmable. Data direction of each port D pin is under the control

of the corresponding bit in data direction register D. Reset has no effect on port D data.

T2CH0 — Timer 2 Channel I/O Bits

The PTD6/T2CH0 pin is the TIM2 input capture/output compare pin. The edge/level select bits,

ELSxB:ELSxA, determine whether the PTD6/T2CH0 pin is a timer channel I/O pin or a

general-purpose I/O pin. See Chapter 22 Timer Interface Module (TIM).

Address:

$000E

Bit 7

432

Bit 0

Read:

000

PTCPUE1

PTCPUE0

Write:

Reset:

000

= Unimplemented

Figure 16-12. Port C Input Pullup Enable Register (PTCPUE)

Address:

$0003

Bit 7

4321

Bit 0

Read:

PTD6

PTD5

PTD4

PTD3

PTD2

PTD1

PTD0

Write:

Reset:

Unaffected by reset

Alternative Function:

T2CH0

T1CH1

T1CH0

SPSCK

MOSI

MISO

= Unimplemented

Figure 16-13. Port D Data Register (PTD)

MC68HC908GR4MP Datasheet(PDF) 152 Page - Freescale Semiconductor, Inc

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