MC68HC908GR4MP datasheet(153/286 Pages) FREESCALE

153 / 286 page

Port D

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

153

T1CH1 and T1CH0 — Timer 1 Channel I/O Bits

The PTD5/T1CH1–PTD4/T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level

select bits, ELSxB and ELSxA, determine whether the PTD5/T1CH1–PTD4/T1CH0 pins are timer

channel I/O pins or general-purpose I/O pins. See Chapter 22 Timer Interface Module (TIM).

SPSCK — SPI Serial Clock

The PTD3/SPSCK pin is the serial clock input of the SPI module. When the SPE bit is clear, the

PTD3/SPSCK pin is available for general-purpose I/O.

MOSI — Master Out/Slave In

The PTD2/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear,

the PTD2/MOSI pin is available for general-purpose I/O.

MISO — Master In/Slave Out

The PTD1/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit,

SPE, is clear, the SPI module is disabled, and the PTD0/SS pin is available for general-purpose I/O.

Data direction register D (DDRD) does not affect the data direction of port D pins that are being used

by the SPI module. However, the DDRD bits always determine whether reading port D returns the

states of the latches or the states of the pins. See Table 16-5.

SS — Slave Select

The PTD0/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the

SPI master bit, SPMSTR, is set, the PTD0/SS pin is available for general-purpose I/O. When the SPI

is enabled, the DDRB0 bit in data direction register B (DDRB) has no effect on the PTD0/SS pin.

16.5.2 Data Direction Register D

Data direction register D (DDRD) determines whether each port D pin is an input or an output. Writing a 1

to a DDRD bit enables the output buffer for the corresponding port D pin; a 0 disables the output buffer.

DDRD6–DDRD0 — Data Direction Register D Bits

These read/write bits control port D data direction. Reset clears DDRD6–DDRD0, configuring all port

D pins as inputs.

1 = Corresponding port D pin configured as output

0 = Corresponding port D pin configured as input

NOTE

Avoid glitches on port D pins by writing to the port D data register before

changing data direction register D bits from 0 to 1.

Address:

$0007

Bit 7

654321

Bit 0

Read:

DDRD6

DDRD5

DDRD4

DDRD3

DDRD2

DDRD1

DDRD0

Write:

Reset:

00000000

= Unimplemented

Figure 16-14. Data Direction Register D (DDRD)

MC68HC908GR4MP Datasheet(PDF) 153 Page - Freescale Semiconductor, Inc

MC68HC908GR4MP Datasheet(HTML) 153 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL